Circuit and method for measuring delay of high speed signals

A method for measuring a time interval between transitions of periodic signals at nodes of a circuit-under-test (CUT), the signals having a periodic clock frequency, comprising:

• periodically latching a digital value of a first periodic signal at edges of an undersampling clock in which the ratio of the undersampling clock frequency to the periodic clock frequency is equal to K±R, where K is an integer, and R is a number between zero and one;
• simultaneously periodically latching a digital value of a second periodic signal at edges of the undersampling clock, the second periodic signal having the same period as the first periodic signal;
• combining latched digital values of said first periodic signal and latched digital values of said second periodic signal to produce a combined output whose duty cycle is proportional to the time interval between a median edge of latched digital values of said first periodic signal and a median edge of latched digital values of said second periodic signal;
• and
• counting the number of undersampling clock cycles in which the combined output is a predetermined logic value within a predetermined time interval whereat said number is proportional to a time interval between a transition of said first periodic signal and a transition of said second periodic signal.