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US 7,453,159 B2Granted
Semiconductor chip having bond pads
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Hee Song, Il-Heung Choi, Jeong-Jin Kim, Hae-Jeong Sohn, Chung-Woo Lee
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Abstract
A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.
Claims24
A semiconductor multi-chip package comprising:
- a package substrate including a surface having a plurality of bonding tips formed thereon;
- and
- two or more semiconductor chips mounted on the package substrate surface, at least one of the chips comprising:
- a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other;
- a bond pad-wiring pattern formed on the semiconductor substrate;
- a pad-rearrangement pattern directly contacting the bond pad-wiring pattern, the pad-rearrangement pattern including bond pads disposed over at least a part of the cell region;
- and
- an insulating layer formed on the pad-rearrangement pattern,
- wherein the bond pad-wiring pattern is formed on at least a part of the peripheral circuit region,
- wherein the bond pads included with the pad-rearrangement pattern is exposed through the insulating layer,
- wherein each bonding tip is electrically connected to a corresponding one of the bond pads.
8 more elements
A semiconductor multi-chip package comprising:
- a package substrate including a surface having a plurality of bonding tips formed thereon;
- and
- three semiconductor chips sequentially mounted on the package substrate surface, an intermediated semiconductor chip comprising:
- a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other;
- a bond pad-wiring pattern formed on the semiconductor substrate;
- a pad-rearrangement pattern directly contacting the bond pad-wiring pattern, the pad-rearrangement pattern including bond pads disposed over at least a part of the cell region;
- and
- an insulating layer formed on the pad-rearrangement pattern,
- wherein the bond pad-wiring pattern is formed on at least a part of the peripheral circuit region,
- wherein the bond pads included with the pad-rearrangement pattern is exposed through the insulating layer,
- wherein each bonding tip is electrically connected to a corresponding one of the bond pads.
8 more elements
A method of forming a semiconductor multi-chip package comprising:
- obtaining two or more semiconductor chips, at least a first chip comprising:
- a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other;
- a bond pad-wiring pattern formed on at least a part of the peripheral circuit region;
- a pad-rearrangement pattern in electrical communication with the bond pad-wiring pattern, the pad-rearrangement pattern including bond pad portions disposed over at least a part of the cell region;
- and
- an insulating layer formed on the pad-rearrangement pattern, and having an opening therein that exposes at least a portion of the pad-rearrangement pattern,
- preparing a package substrate including a surface having a plurality of bonding tips thereon;
- stacking the two or more semiconductor chips on the package substrate;
- forming an electrical connection between at least one bond pad of the first chip and at least one bonding tip;
- and
- forming an electrical connection between at least a second semiconductor chip.
8 more elements
A method for forming a semiconductor multi-chip package comprising:
- preparing a package substrate including a surface having a plurality of bonding tips thereon;
- obtaining three semiconductor chips;
- stacking three semiconductor chips on the package substrate surface, an intermediated semiconductor chip comprising:
- a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other;
- a bond pad-wiring pattern formed on the semiconductor substrate;
- a pad-rearrangement pattern directly contacting the bond pad-wiring pattern, the pad-rearrangement pattern including bond pads disposed over at least a part of the cell region;
- and
- an insulating layer formed on the pad-rearrangement pattern,
- wherein the bond pad-wiring pattern is formed on at least a part of the peripheral circuit region,
- wherein the bond pads included with the pad-rearrangement pattern is exposed through the insulating layer,
- forming an electrical connection between the bond pad and the bonding tips and among the three semiconductor chips;
- and
- encapsulating the surface of the package and the three semiconductor chips.
10 more elements
Dependencies are inferred from the claim text.