Methods for lateral current carrying capability improvement in semiconductor devices

A semiconductor structure, comprising:

• (a) a substrate;
• (b) a first semiconductor device on the substrate;
• (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one;
• (d) a first electrically conductive line electrically coupled to the first semiconductor device,
• wherein the first electrically conductive line is configured to carry a first lateral electric current in a first lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers, and
• wherein the first electrically conductive line is present in both a first ILD layer and a second ILD layer of the N ILD layers;
• (e) a second semiconductor device on the substrate;
• (f) a second electrically conductive line and a third electrically conductive line both being electrically coupled to the second semiconductor device,
• wherein the second electrically conductive line is configured to carry a second lateral electric current in a second lateral direction parallel to the interfacing surface, and
• wherein the third electrically conductive line is configured to carry a third lateral electric current in a third lateral direction parallel to the interfacing surface;
• and
• (g) an electrically connecting via being disposed between and electrically coupling together the second and third electrically conductive lines,
• wherein the electrically connecting via is configured to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface,
• wherein the second electrically conductive line is present in the first ILD layer, and
• wherein both the third electrically conductive line and the electrically connecting via are present in the second ILD layer.