Structure of dielectric layers in built-up layers of wafer level package
AssigneeAdvanced Chip Engineering Technology Inc.
InventorsWen-Kun Yang, Chun-Hui Yu, Chao-Nan Chou, Chih-Wei Lin, Ching-Shun Huang
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AssigneeAdvanced Chip Engineering Technology Inc.
InventorsWen-Kun Yang, Chun-Hui Yu, Chao-Nan Chou, Chih-Wei Lin, Ching-Shun Huang
Estimating the term…
The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.
A structure of a wafer level package, comprising:
Dependencies are inferred from the claim text.