Semiconductor memory device having layout area reduced

A semiconductor memory device comprising:

• a memory array having a plurality of memory cells arranged in a matrix of rows and columns, each including a pair of load transistors of a second conductivity type formed in a first well region of a first conductivity type and a pair of diver transistors of the first conductivity type connected to said load transistors to form a flip-flop, and a plurality of power feed cells, each provided corresponding to a memory cell column, which constitute a row provided to feed said first and second well regions,
• wherein said first and second well regions are alternately disposed in a row direction to extend in a column direction;
• a first power supply line provided corresponding to said plurality of power feed cells along the row direction and electrically coupled to said power feed cell to supply a first power supply voltage to said first well region;
• and
• a second power supply line provided corresponding to said plurality of power feed cells along the row direction and electrically coupled to said power feed cell to supply a second power supply voltage to said second well region,
• wherein said first power supply line is electrically coupled to said first well region through a contact provided for a first metal interconnection layer, and said second power supply line is formed in an upper layer above said first metal interconnection layer and is electrically coupled to said second well region through a plurality of contacts provided for each metal interconnection layer.