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US 7,453,120 B2Granted
Semiconductor structure
AssigneeUnitd Microelectronics Corp.
InventorsShyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
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Abstract
A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.
Claims13
A semiconductor structure, comprising:
- a substrate that has thereon a gate structure and a spacer on a sidewall of the gate structure and has therein a recess beside the spacer;
- an S/D extension region in the substrate beside the gate structure;
- an S/D region in the substrate-surrounding the recess, wherein the S/D region comprises a doped epitaxial layer on the substrate at the bottom of the recess;
- a stress layer over the substrate, a part of the stress layer filled in the recess;
- and
- a metal silicide layer between the S/D region and the stress layer, and between the gate structure and the stress layer.
3 more elements
A semiconductor structure, comprising:
- a substrate;
- a first MOS transistor of a first conductivity type on the substrate, comprising:
- a first gate structure on the substrate;
- a first spacer on a sidewall of the first gate structure, while the substrate has a recess therein beside the first spacer;
- a first S/D extension region of the first conductivity type in the substrate beside the first gate structure;
- and
- a first S/D region of the first conductivity type in the substrate surrounding the recess;
- a second MOS transistor of a second conductivity type on the substrate, comprising:
- a second gate structure on the substrate;
- a second spacer on a sidewall of the second gate structure;
- a second S/D extension region of the second conductivity type in the substrate beside the second gate structure;
- and
- a second S/D region of the second conductivity type in the substrate beside the second spacer;
- a first stress layer over the first MOS transistor, a part of the first stress layer filled in the recess;
- and
- a second stress layer over the second MOS transistor, wherein the first conductivity type is P-type, the second conductivity type is N-type, the first stress layer is a compressive stress layer, the second stress layer is a tensile stress layer, the first S/D region comprises a P-doped SiGe layer on the substrate at the bottom of the recess, and the P-doped epitaxial layer comprises P-doped SiGe.
13 more elements
A semiconductor structure comprising:
- a substrate;
- a first MOS transistor of a first conductivity type on the substrate, comprising:
- a first gate structure on the substrate:
- a first spacer on a sidewall of the first gate structure, while the substrate has a recess therein beside the first spacer;
- a first S/D extension region of the first conductivity type in the substrate beside the first gate structure;
- and
- a first S/D region of the first conductivity type in the substrate surrounding the recess;
- a second MOS transistor of a second conductivity type on the substrate, comprising:
- a second gate structure on the substrate;
- a second spacer on a sidewall of the second gate structure;
- a second S/D extension region of the second conductivity type in the substrate beside the second gate structure;
- and
- a second S/D region of the second conductivity type in the substrate beside the second spacer;
- a first stress layer over the first MOS transistor, a part of the first stress layer filled in the recess;
- and
- a second stress layer over the second MOS transistor, wherein the first conductivity type is N-type, the second conductivity type is P-type, the first stress layer is a tensile stress layer, the second stress layer is a compressive stress layer, the first S/D region comprises an N-doped epitaxial layer on the substrate at the bottom of the recess, and the N-doped epitaxial layer comprises N-doped SiC.
13 more elements
Dependencies are inferred from the claim text.