Non-volatile semiconductor memory device
AssigneeNEC Electronics Corporation
InventorsNaoaki Sudo, Kohji Kanamori
Life of this patent
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Abstract
To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.
Claims15
A non-volatile semiconductor memory device comprising:
- at least two unit cells, wherein each unit cell comprises:
- a memory node provided in a second region adjacent to said first region;
- a diffusion region provided in a third region adjacent to said second region and on the surface of said substrate;
- control gate provided on the top of said memory node;
- and
- a sense amplifier, wherein said two corresponding ones of said unit cells are selectively connected to two input ends of said sense amplifier,
- wherein each data bit being stored uses two of corresponding ones of said unit cells.
A non-volatile semiconductor memory device comprising:
- a plurality of unit cells, wherein one unit cell comprises:
- a select gate provided in a first region on a substrate;
- first and second memory nodes provided in second and third regions on both sides of and adjacent to said first region;
- a diffusion region provided adjacent to said second and third regions and facing said first region;
- and
- a control gate provided on the top of said first and second memory nodes and said select gate;
- and
- a sense amplifier, wherein said two corresponding ones of said units cells are selectively connected to two input ends of said sense amplifier,
- wherein each data bit is stored by having said first and second memory nodes of said unit cell store data having a complementary logic relationship.
A non-volatile semiconductor memory device, comprising:
- at least two unit cells, wherein each unit cell comprises:
- a select gate provided in a first region on a substrate;
- a memory node provided in a second region adjacent to said first region;
- a diffusion region provided in a third region adjacent to said second region and on the surface of said substrate;
- a control gate provided on top of said memory node;
- and
- a sense amplifier, wherein said at least two unit cells are selectively connected to two input ends of said sense amplifier.
Dependencies are inferred from the claim text.