Integrated circuit memory cells and methods of forming

An integrated circuit memory cell comprising:

• a single material forming a combined first capacitor electrode and first transistor source/drain and lacking a material-to-material interface between the first electrode and first source/drain;
• a second capacitor electrode proximate the first electrode;
• a capacitor dielectric between the first and second electrodes;
• a transistor channel directly above the first source/drain;
• another single material forming a combined digit line inner conductor and second transistor source/drain directly above the channel and lacking a material-to-material interface between the digit line inner conductor and second source/drain;
• a conductive barrier material between and in electrical contact with the channel and the inner conductor;
• and
• a digit line portion over and in electrical contact with the inner conductor.

A plurality of integrated circuit memory cells comprising:

• a bulk semiconductor substrate;
• an isolation layer buried in the substrate;
• field isolation in the substrate, the field isolation surrounding and electrically isolating each of a plurality of silicon bases over the isolation layer and within the bulk substrate;
• a plurality of silicon columns extending upward from the plurality of silicon bases, individual columns comprising a combined first capacitor electrode and first transistor source/drain;
• and
• individual memory cells further comprising:
• a second capacitor electrode in common with the plurality of memory cells;
• a capacitor dielectric between the first and second electrodes;
• and
• a vertical transistor above and including the first source/drain.

An integrated circuit memory cell comprising:

• a bulk semiconductor substrate;
• an isolation layer buried in the substrate;
• a combined first capacitor electrode and first transistor source/drain over the substrate lacking a material-to-material interface between the first electrode and first source/drain;
• a second capacitor electrode proximate the first electrode;
• a capacitor dielectric between the first and second electrodes;
• a transistor channel directly above the first source/drain, the channel including a semiconductive upward extension of a material forming the combined first electrode and first source/drain;
• a gate conductor laterally surrounding the channel;
• directly above the channel, a combined second transistor source/drain and digit line inner conductor connecting a digit line to the channel;
• the first and second transistor source/drain, channel, and gate conductor forming a vertical transistor, channel length from the first source/drain to the second source/drain being oriented in a substantially vertical direction with respect to the substrate;
• and
• the memory cell having a straight-line conductive path between the first electrode and the digit line, the path extending through the vertical transistor, and having a cell size of 1.5F×1.5F, where F is feature size of the capacitor dielectric and the first capacitor electrode considered in combination.