Semiconductor device that is advantageous in complex stress engineering and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorZhengwu Jin
Life of this patent
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Abstract
A semiconductor device according to an embodiment includes an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain, a first contact wiring line which is provided on the source, a second contact wiring line which is provided on the drain, and a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines.
Claims17
A semiconductor device comprising:
- an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain;
- a first contact wiring line which is provided on the source;
- a second contact wiring line which is provided on the drain;
- and
- a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines.
A semiconductor device comprising:
- a first insulated-gate field-effect transistor of a first conductivity type including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain;
- a first contact wiring line which is provided on the source;
- a second contact wiring line which is provided on the drain;
- a first piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines;
- and
- a second insulated-gate field-effect transistor of a second conductivity type, which is provided adjacent to the first insulated-gate field-effect transistor in a channel length direction.
Dependencies are inferred from the claim text.