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US 7,453,103 B2Granted
Semiconductor constructions
AssigneeMicron Technology, Inc.
InventorsTodd R. Abbott, H. Montgomery Manning
Life of this patent
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Abstract
The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.
Claims36
A semiconductor construction, comprising:
- a semiconductor substrate comprising a conductively-doped semiconductive material;
- a trenched isolation region within the conductively-doped semiconductive material, the trenched isolation region having a sidewall;
- a bitline between the sidewall of the trenched isolation region and the conductively-doped semiconductive material;
- a dielectric material over the bitline and trenched isolation region;
- a wordline over the dielectric material;
- a vertically-extending pillar proximate the wordline and comprising a channel region vertically between a pair of source/drain regions, the wordline comprising a transistor gate which gatedly connects the source/drain regions to one another through the channel region, one of the source/drain regions being electrically connected to the bitline;
- and
- wherein the vertically-extending pillar comprising the channel and the pair of the source/drain regions is spaced apart from and is not directly over the bitline.
5 more elements
A semiconductor construction, comprising:
- a semiconductor substrate, the semiconductor substrate having a semiconductive material upper surface;
- an isolation region extending into the semiconductor substrate;
- a bitline between the isolation region and the semiconductor substrate;
- a spaced pair of wordlines over the bitline and isolation region, one of the pair of wordlines being a first wordline and the other being a second wordline;
- an electrically insulative line between the spaced pair of the wordlines;
- a first vertically-extending pillar of conductively-doped semiconductor material extending upwardly from the semiconductive material upper surface, the first vertically-extending pillar extending upwardly through the first wordline, the first vertically-extending pillar comprising a first pair of first type source/drain regions on vertically opposed sides of a second type first channel region, one of the first and second types being p-type and the other being n-type, the first pair of the first type source/drain regions being a first source/drain region and a second source/drain region, the first source/drain region being in electrical connection with the bitline, the first vertically-extending pillar being spaced apart from and not directly over the bitline;
- a second vertically-extending pillar of conductively-doped semiconductor material extending upwardly from the semiconductive material upper surface, the second vertically-extending pillar extending upwardly through the second wordline, the second vertically-extending pillar comprising a second pair of first type source/drain regions on vertically opposed sides of a second type second channel region, the second pair of the first type source/drain regions of the second vertically-extending pillar being a third source/drain region and a fourth source/drain region, the third source/drain region being in electrical connection with the bitline, the second vertically-extending pillar being spaced apart from and not directly over the bitline;
- a first gate dielectric around the first verticallypxtendin g pillar and separating the first vertically-extending pillar from the first wordline;
- a second gate dielectric around the second vertically-extending pillar and separating the second vertically-extending pillar from the second wordline;
- a first charge storage device in electrical connection with the second source/drain region;
- and
- a second charge storage device in electrical connection with the fourth source/drain region.
9 more elements
Dependencies are inferred from the claim text.