Thin film transistor panel

A thin film transistor panel comprising:

• a substrate;
• gate lines formed on the substrate;
• data lines insulated from the gate lines and intersecting the gate lines;
• a plurality of thin film transistors connected to the gate lines and the data lines, the thin film transistors each having a drain electrode;
• a plurality of capacitive coupling electrodes each capacitive coupling electrode being associated with and connected to the drain electrode of the associated thin film transistor;
• and
• a plurality of pixel electrodes arranged in a matrix each of the pixel electrodes comprising a first sub-pixel electrode and a second sub-pixel electrode, and each of the pixel electrodes being associated with a pixel area defined by the gate lines and the data lines, wherein the first and second sub-pixel electrodes of each pixel are connected to the drain electrode of the associated thin film transistor, and the second sub-pixel electrode is spaced apart from the first sub-pixel electrode and further wherein the first and second sub-pixel electrodes overlap the capacitive coupling electrodes,
• wherein the second sub-pixel electrodes have a truncated triangular shape and the truncated shorter end in ones of the second sub-pixel electrodes face in a different direction than the truncated shorter ends of other of the second sub-pixel electrodes.

A thin film transistor panel comprising:

• gate lines adapted to transmit scan signals;
• data lines intersecting the gate lines, the data lines being adapted to transmit image signals;
• thin film transistors connected to the gate lines and the data lines, the thin film transistors each having a drain electrode;
• and
• pixel electrodes connected to the drain of electrodes of the thin film transistors formed in pixels surrounded by the gate lines and the data lines,
• wherein the pixel electrodes include first and second sub-pixel electrodes,
• wherein the gate lines include first and second gate lines disposed to correspond to the first and second sub-pixel electrodes,
• wherein the thin film transistors include first and second thin film transistors connecting the first and second sub-pixel electrode, the first and second gate lines, and the data lines,
• wherein the drain electrodes include the first and second drain electrodes, and
• wherein the first sub-pixel electrodes of different pixels are adjacent to each other, and the second sub-pixel electrodes of the different pixels are adjacent to each other.