Negative differential resistance field effect transistor for implementing a pull up element in a memory cell

A pull-up element for a random access memory (RAM) cell, the RAM cell comprising a storage capacitor, the pull-up element comprising a negative differential resistance (NDR) field effect transistor (FET) coupled between the storage capacitor and a high voltage terminal of the RAM cell,

• wherein a junction between the pull-up element and the storage capacitor forms a storage node for the RAM cell, and
• wherein a gate of the NDR FET is coupled to receive a pulsed gate bias signal, the pulsed gate bias signal comprising periodic pulses,
• wherein when a first voltage potential is stored at the storage node, the periodic pulses cause the NDR FET to be turned on, and
• wherein when a second voltage potential is stored at the storage node, the periodic pulses do not cause the NDR FET to be turned on.

A random access memory (RAM) comprising a plurality of memory cells, wherein each of the plurality of memory cells comprises:

• a storage capacitor;
• and
• a negative differential resistance (NDR) field effect transistor (FET) coupled between a high voltage supply terminal and the storage capacitor,
• wherein a junction between the storage capacitor and the NDR FET forms a storage node for the memory cell.