Semiconductor nano-wire devices and methods of fabrication
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Wei Chen, Yee-Chia Yeo, Di-Hong Lee, Fu-Liang Yang, Chenming Hu
Life of this patent
Estimating the term…
Abstract
Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.
Claims21
A method of manufacturing a semiconductor device, the method comprising the steps of:
- providing a semiconductor structure comprising a semiconductor layer overlying an insulating material;
- forming a patterned mask over said semiconductor layer;
- patterning the semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region;
- trimming the patterned mask away from an edge of the semiconductor layer;
- rounding corners of the channel region by annealing while the entire channel region is in direct contact with an underlying support layer;
- and
- removing said patterned mask after said rounding step.
A method of manufacturing a semiconductor device, the method comprising the steps of:
- providing a semiconductor structure comprising a semiconductor layer overlying an insulating material;
- forming a patterned mask over said semiconductor layer;
- patterning the semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region;
- rounding corners of the channel region by annealing, wherein the annealing occurs in an ambient comprising a gas selected from a group consisting essentially of hydrogen, nitrogen, argon, an inert gas, and combinations thereof;
- and
- removing said patterned mask after said rounding step.
A method of manufacturing a semiconductor nano-wire device, the method comprising:
- forming a patterned mask on a semiconductor layer, said semiconductor layer overlying an insulator layer;
- patterning said semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region;
- recessing at least a portion of said patterned mask away from an edge of said semiconductor layer such that said semiconductor layer extends beyond each edge of said patterned mask;
- rounding corners of the channel region by annealing the channel region;
- and
- forming a gate stack comprising a gate electrode overlying a gate dielectric material on a surface of and about the rounded channel region.
A method of manufacturing a semiconductor device, the method comprising the steps of:
- providing a semiconductor structure comprising a semiconductor layer overlying an insulating material;
- forming a patterned mask over said semiconductor layer;
- patterning the semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region;
- rounding corners of the channel region by annealing, wherein the annealing is performed in a vacuum environment at a pressure ranging from about 1.0×10−10 torr to about 1.0×10−3 torr;
- and
- removing said patterned mask after said rounding step.
A method of manufacturing a semiconductor device, the method comprising the steps of:
- providing a semiconductor structure comprising a semiconductor layer overlying an insulating material;
- forming a patterned mask over said semiconductor layer;
- patterning the semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region;
- rounding corners of the channel region by annealing, wherein the annealing is performed in a hydrogen gas environment at about 950 degrees Celsius for about one minute;
- and removing said patterned mask after said rounding step.
Dependencies are inferred from the claim text.