Reduced cell-to-cell shorting for memory arrays
AssigneeMicron Technology, Inc.
InventorKevin R. Shea
Life of this patent
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Abstract
Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.
Claims23
A method of semiconductor fabrication, comprising:
- providing a partially fabricated integrated circuit having a surface comprising a metal nitride and a photoresist;
- and
- subjecting the surface to a wet etch to selectively recess the metal nitride relative to the photoresist,
- wherein the surface further comprises an insulating layer and the metal nitride extends vertically along a vertical wall of the insulating layer,
- wherein the surface further comprises a hemispherical grained silicon layer extending vertically adjacent to the metal nitride and further comprising selectively recessing a hemispherical grained silicon layer after selectively recessing the metal nitride, wherein the hemispherical grained silicon layer is directly adjacent the metal nitride layer.
A method of semiconductor fabrication, comprising:
- providing a partially fabricated integrated circuit having a surface comprising a metal nitride and a photoresist;
- and
- subjecting the surface to a wet etch to selectively recess the metal nitride relative to the photoresist,
- further comprising heating the partially fabricated integrated circuit for about 30to 120 seconds at between about 130° C. and about 250° C. before selectively recessing.
A process for integrated circuit fabrication, comprising:
- providing a partially fabricated integrated circuit having a top surface, the top surface comprising a metal nitride, photoresist and an insulating material, wherein the metal nitride is disposed between the photoresist and the insulating material;
- and
- preferentially etching the metal nitride by exposing the top surface to an ammonium peroxide mixture comprising about 0.33-4.8 weight percent H2O2 and about 0.18-3.9 weight percent NH4OH, or a hydrochloric acid peroxide mixture comprising about 0.33-4.8 weight percent H2O2 and about 0.18-4.9 weight percent HCl.
A process for integrated circuit fabrication,comprising:
- providing a partially fabricated integrated circuit having a top surface, the top surface comprising a metal nitride;
- and
- etching the metal nitride by exposing the top surface to an ammonium peroxide mixture comprising about 0.33-4.8 weight percent H2O2 and about 0.18-3.9 weight percent NH4OH, or a hydrochloric acid peroxide mixture comprising about 0.33-4.8weight percent H2O2 and about 0.18-4.9 weight percent HCl,
- wherein the top surface further comprises photoresist and an insulating material, wherein the metal nitride is disposed between the photoresist and the insulating material,
- wherein etching the metal nitride comprises preferentially etching the metal nitride relative to the photoresist.
Dependencies are inferred from the claim text.