Single event upset in SRAM cells in FPGAs with high resistivity gate structures

A method of providing a single event upset (SEU) resistant memory cell, comprising:

• forming first and second cross-coupled inverters in a substrate, each of the inverters having a gate structure;
• wherein the gate structure comprises a polysilicon layer including two gate electrodes of the inverter and a plug coupled to the polysilicon layer;
• modifying the gate structure to include an SEU-hardening series resistance;
• and
• wherein the modifying of the gate structure includes modifying at least one of the polysilicon layer and the plug;
• wherein modifying the gate structure includes,
• saliciding portions of the polysilicon layer which underlie the plug, and
• masking salicide from a portion of the polysilicon layer which does not underlie the plug to form an unsalicided portion of the polysilicon layer.