Gate-induced strain for MOS performance improvement

A method comprising:

• forming a device on a substrate, the device including a gate electrode on a surface of the substrate and a first junction region and a second junction region in the substrate adjacent the gate electrode;
• forming tip implants adjacent to the first junction region and the second junction region, wherein the tip implants (i) are formed within the substrate, (ii) are situated beneath the gate electrode, and (iii) extend past a sidewall of the gate electrode;
• forming a straining layer on the gate electrode, the straining layer patterned to correspond with a dimension of the gate electrode;
• and
• controlling a thickness of the straining layer relative to a thickness of the gate electrode such that a strain placed on a lattice of the gate electrode is less than ten percent.