Method for a junction field effect transistor with reduced gate capacitance
AssigneeQspeed Semiconductor Inc.
InventorHo-Yuan Yu
Life of this patent
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Abstract
A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches to adjust the lateral dimension for a first gate. Following the formation of the first gate by implantation or deposition, a buffer region is implanted below the first gate using a complementary dopant and a second sidewall spacer with a thickness that may be the same or greater than the thickness of the first sidewall spacer. Subsequent to the buffer implant, a second gate is implanted beneath the buffer layer using a third sidewall spacer with a greater thickness than the first sidewall spacer.
Claims20
A method for fabricating a dual gate structure for a field effect transistor (FET), said method comprising:
- etching a gate trench in a surface of a semiconductor substrate;
- forming a first gate region at the bottom of said gate trench, said first gate region continuous in a lateral direction parallel to said surface;
- implanting a buffer region beneath said first gate region;
- and
- implanting a second gate region beneath said buffer region, wherein said second gate region is formed entirely beneath said first gate region, and wherein, at a conclusion of implanting said second gate region, said second gate region is continuous in said lateral direction and is narrower than said first gate region.
A method for fabricating a dual gate structure for a field effect transistor (FET), said method comprising:
- in sequence,
- etching a gate trench in a surface of a semiconductor substrate;
- forming a first gate region at the bottom of said gate trench;
- implanting a buffer region beneath said first gate region;
- and
- implanting a second gate region beneath said buffer region, wherein said second gate region is formed entirely beneath said first gate region;
- wherein said first gate region and said second gate region together form said dual gate structure.
A method for fabricating a dual gate structure for a field effect transistor (FET), said method comprising:
- etching a gate trench in a surface of a semiconductor substrate;
- forming a first gate region at the bottom of said gate trench;
- after forming the first gate region, implanting a buffer region beneath said first gate region;
- and
- implanting a second gate region beneath said buffer region, wherein said second gate region is formed entirely beneath said first gate region;
- wherein said first gate region and said second gate region together form said dual gate structure.
A method for fabricating a dual gate structure for a field effect transistor (FET), said method comprising:
- etching a gate trench in a surface of a semiconductor substrate;
- forming a first gate region at the bottom of said gate trench;
- implanting a buffer region beneath said first gate region;
- and
- after implanting the buffer region, implanting a second gate region beneath said buffer region, wherein said second gate region is formed entirely beneath said first gate region;
- wherein said first gate region and said second gate region together form said dual gate structure.
Dependencies are inferred from the claim text.