Analog signal processing circuit

Abstract

An analog signal processing block with differential signal inputs and including a differential amplifier with differential inputs is disclosed which is configurable to operate either in a differential output mode or in a single-ended output mode without affecting the desired frequency and time characteristics as determined by the switched capacitor networks. The analog signal processing block includes a pair of switched capacitor networks each having one of the differential signal inputs, an input-sided terminal connected to one of the differential inputs of the differential amplifier and an output-sided terminal. The output-sided terminal of a first one of the switched capacitor networks is connected to an output of the differential amplifier. The output-sided terminal of a second one of the switched capacitor networks is connected to a complementary output of the differential amplifier when configured to differential output mode, and connected to a reference potential when configured to the single-ended mode. In this way, an application can use an analog signal processing block in either of the fully differential and single-ended output modes without the need to reconfigure the switched capacitor networks for a desired frequency and time response characteristic.

Dependencies are inferred from the claim text.