Method of forming vertical FET with nanowire channels and a silicided bottom contact

A method of forming a semiconductor structure comprising:

• forming a silicide contact layer on, or within, a specified region of a semiconductor substrate;
• forming an insulating layer over said silicide contact layer;
• etching openings in said insulating layer;
• forming a plurality of catalyst dots comprised of one of Au, Ga, Al, Ti and Ni in said opening on said silicide contact layer, said plurality of catalysts dots are formed by a self-assembly method or epitaxy;
• forming nanowires from said plurality of catalyst dots, said nanowires are oriented perpendicular to a surface of said semiconductor substrate;
• siliciding a tip of each of said nanowires utilizing a self-aligned silicidation process;
• depositing a gate dielectric and a gate conductor over said nanowires;
• planarizing said nanowires to trim said nanowires to be of same length;
• recessing the gate conductor and forming insulator plugs over said recessed gate conductor;
• and
• forming contacts to an upper surface of each of said nanowires, to said silicide contact layer and to said gate conductor.