Fully lazy linking with module-by-module verification
AssigneeSun Microsystems, Inc.
InventorsGilad Bracha, Sheng Liang, Timothy G. Lindholm
Life of this patent
Estimating the term…
Abstract
A method, computer program, and apparatus verify instructions in a module of a computer program during linking using pre-verification constraints with fully lazy loading. It is first determined whether a first module which is loaded has passed verification one-module-at-a-time before linking. If the first module has passed verification, a pre-verification constraint on a constrained module is read, if any. It is then determined if the constrained module is loaded, if any pre-verification constraint is read. If the constrained module is not already loaded, the pre-verification constraint is retained as a verification constraint.
Claims28
A method for verifying instructions of a module of a computer program during linking, comprising:
- determining whether a first module has passed module-by-module pre-verification;
- reading any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification;
- determining whether the referenced module is loaded based on a determination that a pre-verification constraint is read for the referenced module;
- and
- rewriting the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint.
A method for verifying instructions of a module of a computer program during linking, comprising:
- determining whether a first module has passed module-by-module pre-verification;
- reading any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification;
- determining whether the referenced module is loaded based on a determination that a pre-verification constraint is read for the referenced module;
- enforcing the pre-verification constraint based on a determination that the referenced module is loaded;
- and
- rewriting the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint.
A method for verifying instructions of a module of a computer program during linking, comprising:
- reading a pre-verification constraint on a referenced module;
- determining whether the referenced module is loaded;
- rewriting the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint;
- retaining the pre-verification constraint as a verification constraint based on a determination that the referenced module is not loaded;
- and
- enforcing the retained pre-verification constraint when the referenced module is loaded.
An apparatus for verifying instructions of a module, comprising:
- a memory including a program that
- determines whether a first module has passed module-by-module pre-verification;
- reads any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification;
- determines whether the referenced module is loaded to the memory based on a determination that a pre-verification constraint is read for the referenced module;
- and
- rewrites the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification;
- and
- a processor that runs the program.
An apparatus for verifying instructions of a module, comprising:
- a memory including a program that
- determines whether a first module has passed module-by-module pre-verification;
- reads any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification;
- determines whether the referenced module is loaded to the memory based on a determination that a pre-verification constraint is read for the referenced module;
- enforces the pre-verification constraint based on a determination that the referenced module is loaded;
- and
- rewrites the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint;
- and
- a processor that runs the program.
An apparatus for verifying instructions of a module, comprising:
- a memory including a program that
- reads a pre-verification constraint on a referenced module;
- determines whether the referenced module is loaded;
- rewrites the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint;
- retains the pre-verification constraint as a verification constraint based on a determination that the referenced module is not loaded;
- and
- enforces the retained pre-verification constraint when the referenced module is loaded;
- and
- a processor that runs the program.
A computer-readable storage medium containing instructions for performing a method for verifying instructions of a module, the method comprising:
- determining whether a first module has passed module-by-module pre-verification;
- reading any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification;
- determining whether the referenced module is loaded based on a determination that a pre-verification constraint is read for the referenced module;
- and
- rewriting the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint.
A computer-readable storage medium containing instructions for performing a method for verifying instructions of a module, the method comprising:
- determining whether a first module has passed module-by-module pre-verification;
- reading any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification;
- determining whether the referenced module is loaded based on a determination that a pre-verification constraint is read for the referenced module;
- enforcing the pre-verification constraint based on a determination that the referenced module is loaded;
- and
- rewriting the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint.
A computer-readable storage medium containing instructions for performing a method for verifying instructions of a module, the method comprising:
- reading a pre-verification constraint on a referenced module;
- determining whether the referenced module is loaded;
- rewriting the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint;
- retaining the pre-verification constraint as a verification constraint based on a determination that the referenced module is not loaded;
- and
- enforcing the retained pre-verification constraint when the referenced module is loaded.
An apparatus for verifying instructions of a module of a computer program during linking, comprising:
- a memory having a program that determines whether a first module has passed module-by-module pre-verification, reads any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification, determines whether the referenced module is loaded based on a determination that a pre-verification constraint is read for the referenced module, and rewrites the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint;
- and
- a processor that runs the program.
An apparatus for verifying instructions of a module of a computer program during linking, comprising:
- a memory having a program that determines whether a first module has passed module-by-module pre-verification, reads any pre-verification constraints on a referenced module based on a determination that the first module passed module-by-module pre-verification, determines whether the referenced module is loaded based on a determination that a pre-verification constraint is read for the referenced module, enforces the pre-verification constraint based on a determination that the referenced module is loaded, and rewrites the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint;
- and
- a processor that runs the program.
An apparatus for verifying instructions of a module of a computer program during linking, comprising:
- a memory having a program that reads a pre-verification constraint on a referenced module, determines whether the referenced module is loaded, rewrites the pre-verification constraint as a verification constraint based on a determination that the referenced module conditionally passed enforcement of the pre-verification constraint, retains the pre-verification constraint as a verification constraint based on a determination that the referenced module is not loaded, and enforces the retained pre-verification constraint when the referenced module is loaded;
- and
- a processor that runs the program.
Dependencies are inferred from the claim text.