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US 7,444,630 B2Granted
Method and apparatus for changing microcode to be executed in a processor
AssigneeSTMicroelectronics S.r.l.
InventorChristian D. Kasper
Life of this patent
Estimating the term…
Abstract
A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.
Claims23
A hot patch system comprising:
- a read only memory storing a plurality of instructions;
- a cache memory storing alternate instructions for at least one instruction stored within the read only memory, each cache line within the cache memory having associated therewith one or more selection flags;
- a program counter coupled to the read only memory and to the cache memory, the program counter transmitting an address to both the read only memory and the cache memory;
- and
- cache control logic coupled to the cache memory, the cache control logic comparing selected information associated with an instruction stored at the address in the read only memory with counterpart selected information associated with an instruction stored at the address in the cache memory, wherein the selected information and counterpart selected information are selected based upon the one or more selection flags associated with a cache line corresponding to the address.
2 more elements
A hot patch method comprising:
- storing a plurality of instructions within a read only memory;
- storing alternate instructions for at least one instruction in the read only memory within a cache memory, each cache line within the cache memory having associated therewith one or more selection flags;
- transmitting an address to both the read only memory and the cache memory;
- and
- comparing selected information associated with an instruction stored at the address in the read only memory with counterpart selected information associated with an instruction stored at the address in the cache memory, wherein the selected information and counterpart selected information are selected based upon the one or more selection flags associated with a cache line corresponding to the address.
2 more elements
A hot patch system comprising:
- a read only memory storing a plurality of instructions;
- a cache memory storing alternate instructions for at least one instruction stored within the read only memory, each cache line within the cache memory having associated therewith one or more selection flags and one or more instruction flow control flags;
- and
- cache control logic coupled to the cache memory, the cache control logic comparing selected information associated with an instruction stored at a specified address in the read only memory with counterpart selected information associated with an instruction stored at the specified address in the cache memory,
- wherein the selected information and counterpart selected information are selected based upon the one or more selection flags associated with a cache line corresponding to the specified address, and
- wherein the cache control logic causes a change in instruction flow based upon the one or more instruction flow control flags associated with the cache line corresponding to the address when there is a comparison match between the selected information and the counterpart selected information.
3 more elements
Dependencies are inferred from the claim text.