Calibration on wafer sweet spots
AssigneeInvarium, Inc.
InventorsGokhan Percin, Ram S. Ramanujam, Franz X. Zach, Abdurrahman Sezginer, Chi-Song Horng, Roy Prasad
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Abstract
A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
Claims25
A method of generating an OPC computational model comprises:
- a. printing test patterns at multiple sites of a wafer;
- b. measuring properties of the test patterns printed at multiple sites on the said wafer;
- c. extracting an across-wafer component of the measured properties, the component being a continuous function of position on the wafer;
- d. selecting a location on the wafer, wherein a gradient of the across-wafer component is minimum;
- and
- e. adjusting parameters of the computational model to minimize the difference between the predictions of the model and the measurements taken in the said selected spot.
A method of generating an OPC computational model comprises:
- a. printing test patterns at multiple sites of a wafer;
- b. measuring properties of the test patterns printed at multiple sites on the said wafer;
- c. extracting an across-wafer component of the measured properties, the component being a continuous function of position on the wafer;
- d. separating the variations in the measurement made in step (b) into an across-wafer variation and other components of variation;
- e. selecting a location on the wafer, wherein a gradient of an across-wafer component is minimum;
- f. printing at least one test targets on the said location;
- g. measuring properties of the said test targets selected in the said location, and
- h. adjusting parameters of the computational model to minimize the difference between the predictions of the model and the measurements taken in the said selected spot.
A method of calibrating a computational model of a patterning process, said method comprising:
- a. printing test patterns at multiple sites of a wafer;
- b. measuring a critical dimension of the test patterns printed at multiple sites on the said wafer;
- c. extracting an across-wafer component of the variation in the critical dimension measurements, the component being a continuous function of position on the wafer;
- d. selecting a sweet-spot on the wafer where the gradient of the across-wafer component is small;
- e. adjusting a parameter of the computational model so that the difference between a prediction of the model and a measurement performed in the sweet spot is minimized.
Dependencies are inferred from the claim text.