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AssigneeAltera Corporation
InventorsGordon Chiu, Deshanand Singh, Valavan Manohararajah, Stephen Brown
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Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.
A method for mapping logic functions implemented in logic elements into synchronous embedded memory blocks comprising:
A method for mapping logic functions implemented in logic elements into synchronous embedded memory blocks comprising:
A system for mapping logic functions implemented in logic elements into synchronous embedded memory blocks wherein the system comprises:
A system for mapping logic functions implemented in logic elements into synchronous embedded memory blocks wherein the system comprises:
Dependencies are inferred from the claim text.