Method for correcting timing error when designing semiconductor integrated circuit

A method for correcting a hold error in an integrated circuit that includes a plurality of layout blocks including first and second layout blocks with identical configurations in a same hierarchical layer, wherein the first layout block includes a first cell corresponding to a second cell of the second layout block, each of the first and second cells having a tolerance for when a setup error occurs, the method comprising:

• determining a worst condition and one of the first and second cells that has the worst condition;
• matching the tolerances of the first and second cells in the first and second layout blocks with the worst condition of the determined one of the first and second cells;
• and
• inserting a delay cell in each of the first and second layout blocks within a range of the matched tolerance of the first and second cells in the first and second layout blocks to adjust a hold error.

A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in a same hierarchical layer, wherein each layout block includes a path, the method comprising:

• determining whether timing error occurs in a relatively small number of layout blocks;
• specifying a layout block, among the plurality of layout blocks, including a path having a timing error if it is determined that there are timing errors in a relatively small number of layout blocks;
• and
• inserting a timing adjustment cell in the specified layout block to adjust a timing error.

A method for correcting a hold error in an integrated circuit that includes a plurality of layout blocks with identical configurations in a same hierarchical layer, wherein each layout block includes a path, the method comprising:

• determining whether hold error occurs in a relatively small number of layout blocks;
• specifying a layout block, among the plurality of layout blocks, including a path having a hold error if it is determined that there are hold errors in a relatively small number of layout blocks;
• and
• inserting a delay cell in the specified layout block to adjust a hold error.

A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in a same hierarchical layer, wherein each layout block has a cell, corresponding to a cell of another layout block, and a path of the cell, the cell of each layout block having a tolerance for when a timing error occurs, the method comprising:

• determining a number of layout blocks, among the plurality of layout blocks, including a path having a timing error and whether the number of layout blocks is relatively large or small;
• if the number of layout blocks is relatively large:
• determining a worst condition and one of corresponding cells that has the worst condition, and matching tolerances of corresponding cells in layout blocks with the worst condition of the determined one of the corresponding cells;
• and
• inserting a timing adjustment cell within a range of the matched tolerance of each cell to adjust the timing error;
• if the number of layout blocks is relatively small;
• specifying the layout block including a path having a timing error;
• and
• inserting a timing adjustment cell in the specified layout block to adjust the timing error.

A method for correcting a hold error in an integrated circuit that includes a plurality of layout blocks with identical configurations in a same hierarchical layer, wherein each layout block has a cell, corresponding to a cell of another layout block, and a path of the cell, the cell of each layout block having a tolerance for when a setup error occurs, the method comprising:

• determining a number of layout blocks, among the plurality of layout blocks, including a path having a timing error and whether the number of layout blocks is relatively large or small;
• if the number of layout blocks is relatively large:
• determining a worst condition and one of the corresponding cells that has the worst condition, and matching tolerances of corresponding cells in layout blocks with the worst condition of the determined one of corresponding cells;
• and
• inserting a delay cell within a range of the matched tolerance of the corresponding cell in each layout block to adjust a hold error;
• if the number of layout blocks is relatively small:
• specifying the layout block, among the plurality of layout blocks, that includes a path having the hold error;
• and
• inserting a delay cell in the specified layout block to adjust the hold error.

A method correcting a timing error, comprising:

• comparing delay times of a plurality of cells in a plurality of layout blocks, wherein each of the plurality cells has a tolerance for when a timing error occurs;
• matching the tolerance of the plurality of cells with a worst condition;
• and
• inserting a delay cell in one of the plurality of layout blocks within a range of the matched tolerance of the plurality of cells to adjust timing error.