Method for designing semiconductor integrated circuit, semiconductor integrated circuit and program for designing same

A method for designing a semiconductor integrated circuit comprising:

• a lower hierarchy design step of independently designing a plurality of circuit blocks each having a plurality of flip-flops that are reset in response to activation transition of a reset signal from a reset input pin;
• and
• an upper hierarchy design step of designing an entire semiconductor integrated circuit having the plurality of circuit blocks, wherein:
• said lower hierarchy design step comprises:
• a first step of inserting a reset adjustment circuit immediately after the reset input pin in each of the circuit blocks, the reset adjustment circuit propagating deactivation transition of the reset signal to the flip-flops in synchronization with a clock signal supplied to the flip-flops;
• and
• a second step of implementing delay time adjustment for paths of the reset signal, using the clock signal as a reference, the paths extending from the reset adjustment circuit to the flip-flops;
• and
• said upper hierarchy design step comprises a third step of implementing timing adjustment for paths of the reset signal using the clock signal as a reference according to setup times and hold times of the reset signal that are prescribed respectively for the reset input pins of the circuit blocks, the paths extending to the reset input pins of the circuit blocks.

A semiconductor integrated circuit comprising:

• a plurality of flip-flops that are reset in response to activation transition of a reset signal from a reset input pin;
• a reset adjustment circuit provided immediately after the reset input pin and propagating deactivation transition of the reset signal to said flip-flops in synchronization with a clock signal supplied to said flip-flops;
• and
• a first delay time adjustment circuit adjusting delay times of paths of the reset signal, using the clock signal as a reference, the paths extending from said reset adjustment circuit to said flip-flops.

A semiconductor integrated circuit comprising:

• a plurality of circuit blocks each comprising:
• a plurality of flip-flops that are reset in response to activation transition of a reset signal from a reset input pin;
• a reset adjustment circuit provided immediately after the reset input pin and propagating deactivation transition of the reset signal to the flip-flops in synchronization with a clock signal supplied to the flip-flops;
• and
• a first delay time adjustment circuit adjusting delay times of paths of the reset signal according to the clock signal, the paths extending from the reset adjustment circuit to the flip-flops;
• and
• a second delay time adjustment circuit adjusting delay times of paths of the reset signal using the clock signal as a reference according to setup times and hold times of the reset signal that are prescribed respectively for the reset input pins of the circuit blocks, the paths extending to reset input pins of the circuit blocks.

A program for designing a semiconductor integrated circuit, comprising:

• a lower hierarchy design step of causing a computer for designing a semiconductor integrated circuit to independently design a plurality of circuit blocks each of which has a plurality of flip-flops that are reset in response to activation transition of a reset signal from a reset input pin;
• and
• an upper hierarchy design step of causing the computer to design an entire semiconductor integrated circuit having the plurality of circuit blocks, wherein:
• said lower hierarchy design step includes a first step of causing the computer to insert a reset adjustment circuit immediately after the reset input pin in each of the circuit blocks, the reset adjustment circuit propagating deactivation transition of the reset signal to the flip-flops in synchronization with a clock signal supplied to the flip-flops;
• and a second step of causing the computer to implement timing adjustment for paths of the reset signal, using the clock signal as a reference, the paths extending from the reset adjustment circuit to the flip-flops;
• and
• said upper hierarchy design step includes a third step of causing the computer to implement timing adjustment for paths of the reset signal using the clock signal as a reference according to setup times and hold times of the reset signal that are prescribed respectively for the reset input pins of the circuit blocks, the paths extending to the reset input pins of the circuit blocks.