Non-systematic coded error correction

A memory device comprising:

• a memory array containing a plurality of memory cells arranged into a plurality of segments;
• a data buffer;
• a host transfer circuit coupled to the data buffer;
• an ECC generator/checker circuit, wherein ECC generator/checker circuit is adapted to receive and decode a non-systematic ECC encoded data segment from the memory array and output to the data buffer;
• and
• wherein the memory device is adapted to detect and correct errors in the non-systematic ECC encoded data segment as it is read from the memory array.

A Flash memory system, comprising:

• at least one Flash memory device, wherein the at least one Flash memory device contains a memory array with a plurality of floating gate memory cells arranged into a plurality of sectors in a plurality of erase blocks, wherein each erase block of the plurality of erase blocks contains a plurality of physical row pages, each physical row page containing one or more data sectors;
• a Flash memory control circuit coupled to the at least one Flash memory device, wherein
• the Flash memory control circuit comprises,
• a data buffer,
• a host transfer circuit coupled to the data buffer,
• an ECC generator/checker circuit, wherein ECC generator/checker circuit is adapted to receive and decode a non-systematic ECC encoded data sector from the at least one Flash memory device and output to the data buffer;
• and
• wherein the Flash memory system is adapted to detect and correct errors in the non-systematic ECC encoded data sector as it is read from the at least one memory device.

A memory controller comprising:

• a host interface;
• a memory device interface for one or more memory devices, wherein each of the one or more memory devices has a plurality of segments;
• a data buffer coupled to the memory device interface;
• a host transfer circuit coupled to the data buffer and to the host interface;
• an ECC generator/checker circuit, wherein ECC generator/checker circuit is adapted to receive and decode a selected non-systematic ECC encoded data segment from the at least one memory device and output to the data buffer;
• and
• wherein the memory controller is adapted to detect and correct errors the selected non-systematic ECC encoded data segment as it is read from the at least one memory device.

A system comprising:

• a host coupled to a memory system, wherein the memory system comprises:
• at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments;
• a memory control circuit coupled to the at least one memory device, wherein the
• memory control circuit comprises,
• a data buffer,
• a host transfer circuit coupled to the data buffer, and
• an ECC generator/checker circuit, wherein ECC generator/checker circuit is adapted to receive a non-systematic ECC encoded data segment from the at least one memory device and output to the data buffer;
• and
• wherein the memory system is adapted to detect and correct errors in the non-systematic ECC encoded data segment as it is read from the at least one memory device.

A memory system, comprising:

• at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments;
• a memory control circuit coupled to the at least one memory device, wherein the memory
• control circuit comprises,
• a data buffer coupled to receive a non-systematic ECC encoded data segment from the at least one memory device,
• a host transfer circuit, and
• an ECC generator/checker circuit, wherein ECC generator/checker circuit is coupled to the data buffer and to the host transfer circuit;
• and
• wherein the ECC generator/checker is adapted to error check and decode the non-systematic ECC encoded data segment as it is transferred from the memory system through the host transfer circuit.