Architecture and method for testing of an integrated circuit device
AssigneeInapac Technology, Inc.
InventorAdrian E. Ong
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.
Claims54
A system comprising:
- a first integrated circuit device;
- a second integrated circuit device implemented on a first monolithic die and connected to the first integrated circuit device, wherein the first and second integrated circuit devices operate in conjunction in a normal operation;
- and
- a testing component implemented on a second monolithic die and operable to be connected between an external test machine and the second integrated circuit device for testing of the second integrated circuit in a test mode, wherein the testing component allows the external test machine to test the second integrated circuit device in the test mode.
A system comprising:
- a first integrated circuit device implemented on a first monolithic die;
- a second integrated circuit device implemented on the first monolithic die and connected to the first integrated circuit device, wherein the second integrated circuit device communicates with the first integrated circuit device to process information during a normal operation;
- and
- a testing component operable to be connected between an external test machine and the second integrated circuit device for testing of the second integrated circuit in a test mode, wherein the testing component is implemented on a second monolithic die, wherein the testing component allows the external test machine to test the second integrated circuit device during a test mode.
A system comprising:
- a first integrated circuit device implemented on a first monolithic die;
- a second integrated circuit device implemented on a second monolithic die and connected to the first integrated circuit device, wherein the first and second integrated circuit devices operate in conjunction in a normal operation;
- a testing component operable to be connected between an external test machine and the second integrated circuit device for testing of the second integrated circuit in a test mode, wherein the testing component allows the external test machine to test the second integrated circuit device in a test mode.
A testing component for testing of a system comprising a first integrated circuit device connected to and operable to operate in conjunction with a second integrated circuit device, wherein the first integrated circuit device is implemented on a first monolithic die and the second integrated circuit device is implemented on a second monolithic die, the testing component comprising:
- circuitry for receiving bits of test data from an external test machine at a first frequency;
- circuitry for generating a string of bits for each bit of test data from the external test machine;
- and
- circuitry for providing the generated bit strings to the second integrated circuit device at a second frequency, wherein the second frequency is higher than the first frequency.
Dependencies are inferred from the claim text.