US 7,444,573 B2Granted

VLCT programmation/read protocol

AssigneeTexas Instruments Incorporated

InventorsRaguram Damodaran, Ananthakrishnan Ramamurti, Ravi Lakshmanan

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Abstract

An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address. The data transfer count corresponds to the amount of data transferred and the number of cycle in the data access phase. The data access phase begins by accessing the data register corresponding to the address from the command phase. During subsequent cycles of the data access phase, the external tester accesses sequential data registers. The programmable built-in self test unit includes a pointer register and an adder to update the address each cycle of the data phase.

Claims6

Dependent claims

An integrated circuit comprising:

a plurality of operational circuits to be tested;
a test read only memory storing at least one test set consisting of a test algorithm and test data;
an external tester interface;
and
a programmable built-in self test unit connected to said plurality of operational circuits to be tested, said test read only memory and said external tester interface, said programmable built-is self test unit including
a plurality of read and write read and write data registers,
a pointer register storing a pointer indicating one of said plurality of read and write read and write data registers,
an adder having a first input connected to said pointer register, a second input receiving data equal to +1 and an output connected to said pointer register;
and
wherein said programmable built-in self test unit is operable to
load from said test read only memory operable for each test set stored in said test read only memory said test algorithm and said test data,
test at least one of said plurality of operational circuits to be tested according to said test algorithm and said test data loaded,
enable access to said data registers indicated by said pointer register and increment said pointer register by said adder when in a tester access mode.

10 more elements

Dependencies are inferred from the claim text.