Apparatus and method for testing and debugging an integrated circuit

A system for testing a target integrated circuit, comprising:

• a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the target integrated circuit and that analyzes received data from the target integrated circuit;
• a first interface module that communicates with said host device and that formats said test instructions and data using a first format;
• a first serializer that serializes said formatted test instructions and data;
• a first deserializer on said target integrated circuit that communicates with said first serializer and that deserializes said test instructions and data;
• and
• a control module on the target integrated circuit that communicates with said first deserializer, that interprets said test instructions and data using said first format, that includes a testing module that receives said interpreted test instructions and data from said control module and that performs testing and debugging of said target integrated circuit;
• a frame capture module on said target integrated circuit that receives test results;
• a first control module that communicates with said frame capture module and that generates first format control data for said first interface module, wherein said frame capture module packages at least one of said test results and said first format control data into frames;
• and
• a second serializer that serializes said frames from said frame capture module,
• wherein said second serializer operates a rate that is higher than a rate of said first serializer.

A system for testing a target integrated circuit, comprising:

• a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the target integrated circuit and that analyzes received data from the target integrated circuit;
• a first interface module that communicates with said host device and that formats said test instructions and data using a first format;
• a first serializer that serializes said formatted test instructions and data;
• a first deserializer on said target integrated circuit that communicates with said first serializer and that deserializes said test instructions and data;
• and
• a control module on the target integrated circuit that communicates with said first deserializer, that interprets said test instructions and data using said first format, that includes a testing module that receives said interpreted test instructions and data from said control module and that performs testing and debugging of said target integrated circuit;
• a frame capture module on said target integrated circuit that receives test results;
• a first control module that communicates with said frame capture module and that generates first format control data for said first interface module, wherein said frame capture module packages at least one of said test results and said first format control data into frames;
• a second serializer that serializes said frames from said frame capture module;
• a second deserializer that communicates with said second serializer and that deserializes said frames;
• and
• a frame sync module that receives said deserialized frames and that synchronizes said frames,
• wherein said frame sync module forwards control frames to said first interface module.

A system for testing a target integrated circuit, comprising:

• a host device that executes a debugging and testing analysis program, that transmits test instructions and data to the target integrated circuit and that analyzes received data from the target integrated circuit;
• a first interface module that communicates with said host device and that formats said test instructions and data using a first format;
• a first serializer that serializes said formatted test instructions and data;
• a first deserializer on said target integrated circuit that communicates with said first serializer and that deserializes said test instructions and data;
• and
• a control module on the target integrated circuit that communicates with said first deserializer, that interprets said test instructions and data using said first format, that includes a testing module that receives said interpreted test instructions and data from said control module and that performs testing and debugging of said target integrated circuit;
• a frame capture module on said target integrated circuit that receives test results;
• a first control module that communicates with said frame capture module and that generates first format control data for said first interface module, wherein said frame capture module packages at least one of said test results and said first format control data into frames;
• a second serializer that serializes said frames from said frame capture module;
• a second deserializer that communicates with said second serializer and that deserializes said frames;
• a frame sync module that receives said deserialized frames and that synchronizes said frames;
• and
• a diagnostic module that receives at least one of digital control, state and/or error data from said frame sync module.

A method for testing a target integrated circuit, comprising:

• executing a debugging and testing analysis program;
• transmitting test instructions and data to the target integrated circuit and analyzing received data from the target integrated circuit;
• formatting said test instructions and data using a first format at a test interface module;
• serializing said formatted test instructions and data at a serializer that is separate from said first interface module;
• deserializing said test instructions and data;
• and
• interpreting said test instructions and data using said first format;
• and
• performing testing and debugging of said target integrated circuit.

A method for testing a target integrated circuit, comprising:

• executing a debugging and testing analysis program;
• transmitting test instructions and data to the target integrated circuit and analyzing received data from the target integrated circuit;
• formatting said test instructions and data using a first format;
• serializing said formatted test instructions and data;
• deserializing said test instructions and data;
• interpreting said test instructions and data using said first format;
• performing testing and debugging of said target integrated circuit;
• receiving test results;
• generating first format control data;
• packaging at least one of said test results and said first format control data into frames;
• serializing said frames;
• deserializing said frames;
• receiving said deserialized frames and synchronizing said frames;
• and
• forwarding control frames.

A method for testing a target integrated circuit, comprising:

• executing a debugging and testing analysis program;
• transmitting test instructions and data to the target integrated circuit and analyzing received data from the target integrated circuit;
• formatting said test instructions and data using a first format;
• serializing said formatted test instructions and data;
• deserializing said test instructions and data;
• interpreting said test instructions and data using said first format;
• performing testing and debugging of said target integrated circuit;
• receiving test results;
• generating first format control data;
• packaging at least one of said test results and said first format control data into frames;
• serializing said frames;
• deserializing said frames;
• receiving said deserialized frames and synchronizing said frames;
• receiving at least one of digital control, state and/or error data;
• and
• converting said at least one of said digital control, state and/or error data to at least one of analog control, state and/or error data.

A system for testing a target integrated circuit, comprising:

• host means for executing a debugging and testing analysis program, for transmitting test instructions and data to the target integrated circuit and for analyzing received data from the target integrated circuit;
• first interface means for communicating with said host means and for formatting said test instructions and data using a first format;
• first serializer means for serializing said formatted test instructions and data that is separate from said first interface means;
• first deserializer means on said target integrated circuit for communicating with said first serializer means and for deserializing said test instructions and data;
• and
• control means on the target integrated circuit for communicating with said first deserializer means and for interpreting said test instructions and data using said first format and that includes testing means for receiving said interpreted test instructions and data from said control means and for performing testing and debugging of said target integrated circuit.

A system for testing a target integrated circuit, comprising:

• host means for executing a debugging and testing analysis program, for transmitting test instructions and data to the target integrated circuit and for analyzing received data from the target integrated circuit;
• first interface means for communicating with said host means and for formatting said test instructions and data using a first format;
• first serializer means for serializing said formatted test instructions and data;
• first deserializer means on said target integrated circuit for communicating with said first serializer means and for deserializing said test instructions and data;
• and
• control means on the target integrated circuit for communicating with said first deserializer means and for interpreting said test instructions and data using said first format and that includes testing means for receiving said interpreted test instructions and data from said control means and for performing testing and debugging of said target integrated circuit;
• frame capture means on said target integrated circuit for receiving test results;
• first control means for communicating with said frame capture means and for generating first format control data for said first interface means, wherein said frame capture means packages at least one of said test results and said first format control data into frames;
• and
• second serializing means for serializing said frames from said frame capture means,
• wherein said second serializing means operates at a rate that is higher than a rate of said first serializer means.

A system for testing a target integrated circuit, comprising:

• host means for executing a debugging and testing analysis program, for transmitting test instructions and data to the target integrated circuit and for analyzing received data from the target integrated circuit;
• first interface means for communicating with said host means and for formatting said test instructions and data using a first format;
• first serializer means for serializing said formatted test instructions and data;
• first deserializer means on said target integrated circuit for communicating with said first serializer means and for deserializing said test instructions and data;
• and
• control means on the target integrated circuit for communicating with said first deserializer means and for interpreting said test instructions and data using said first format and that includes testing means for receiving said interpreted test instructions and data from said control means and for performing testing and debugging of said target integrated circuit;
• frame capture means on said target integrated circuit for receiving test results;
• first control means for communicating with said frame capture means and for generating first format control data for said first interface means, wherein said frame capture means packages at least one of said test results and said first format control data into frames;
• second serializing means for serializing said frames from said frame capture means;
• second deserializer means for communicating with said second serializer means and for deserializing said frames;
• and
• frame sync means for receiving said deserialized frames and for synchronizing said frames,
• wherein said frame sync means forwards control frames to said first interface means.

A system for testing a target integrated circuit, comprising:

• host means for executing a debugging and testing analysis program, for transmitting test instructions and data to the target integrated circuit and for analyzing received data from the target integrated circuit;
• first interface means for communicating with said host means and for formatting said test instructions and data using a first format;
• first serializer means for serializing said formatted test instructions and data;
• first deserializer means on said target integrated circuit for communicating with said first serializer means and for deserializing said test instructions and data;
• and
• control means on the target integrated circuit for communicating with said first deserializer means and for interpreting said test instructions and data using said first format and that includes testing means for receiving said interpreted test instructions and data from said control means and for performing testing and debugging of said target integrated circuit;
• frame capture means on said target integrated circuit for receiving test results;
• first control means for communicating with said frame capture means and for generating first format control data for said first interface means, wherein said frame capture means packages at least one of said test results and said first format control data into frames;
• second serializing means for serializing said frames from said frame capture means;
• second deserializer means for communicating with said second serializer means and for deserializing said frames;
• and
• frame sync means for receiving said deserialized frames and for synchronizing said frames;
• and
• diagnostic means for receiving at least one of digital control, state and/or error data from said frame sync means.