Apparatus and method for controlling frequency of an I/O clock for an integrated circuit during test

A test system, comprising:

• a device under test, comprising:
• input/output (I/O) interface logic which receives an external bus clock signal having a first frequency, which receives and operates according to a pad clock signal, and which is configured to detect a test mode and to internally provide a test signal if said test mode is detected;
• and
• a clock circuit, coupled to said I/O interface logic, comprising:
• a core clock circuit which generates a core clock signal at a second frequency based on said bus clock signal and a first clock ratio value;
• a pad clock circuit which generates a preliminary clock signal at a third frequency based on said bus clock signal and a second clock ratio value;
• a test clock circuit which generates a test clock signal at a fourth frequency based on said first frequency, said second clock ratio value and a third clock ratio value in which said fourth frequency is suitable for operating said I/O interface logic during said test mode;
• and
• a select circuit which selects, based on said test signal, between said test clock signal and said preliminary clock signal as said pad clock signal;
• and
• a tester for testing said device under test, which provides said bus clock signal and which indicates said test mode to said device under test via said I/O interface logic.

A method of testing an integrated circuit (IC), the IC having a clock input for receiving a bus clock signal up to a first frequency, internal core circuitry operative up to a second frequency which is a first multiple of said first frequency, and an input/output (I/O) interface operative up to a third frequency which is a second multiple of said first frequency, said method comprising:

• providing the bus clock signal to the IC at the first frequency and providing the first multiple to the IC to enable operation of the internal core circuitry up to the second frequency;
• programming the IC to operate in a test mode via the I/O interface;
• providing a test clock signal at a fourth frequency which is reduced relative to the third frequency by a third multiple;
• and
• providing the test clock signal to the I/O interface within the IC when in the test mode.