Semiconductor integrated circuit having test circuitry with reduced power consumption

Abstract

The present invention provides a semiconductor integrated circuits that can prevent causes arising a problem of the power consumption during the normal operation thereof. Solution: The present invention relates to a semiconductor integrated circuit having a plurality of memory device of the scan thereof having functions to output the status values during the scan test therein. At least, a part of the memory device of the scan includes a first signal-outputting unit outputting a signal during the normal operation therein and a second signal-outputting unit outputting a signal during the scan test operation therein, respectively. Where, it is preferable that the first signal-outputting unit has a larger driving capacity to signal lines therein than the second signal-outputting unit, and that a second signal-outputting unit fixes the output signal level during the normal operation thereof, and that the second signal-outputting unit outputs a status value delayed a predetermined period of the operation clock therein compared with the first signal-outputting unit during the scan test thereof, and so on.

Dependencies are inferred from the claim text.