Method and apparatus for testing a data processing system
AssigneeFreescale Semiconductor, Inc.
InventorsGary R. Morrison, Jose A. Lyon, William C. Moyer, Anthony M. Reipold
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Abstract
A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.
Claims25
A method for testing at least one logic block of a processor, comprising:
- during execution of a user application by the processor, the processor generating a stop and test indicator, in response to the generation of the stop and test indicator stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor;
- and
- applying a test stimulus for testing the at least one logic block of the processor.
An apparatus for testing at least one logic block of a processor, comprising:
- a test controller configured to, during execution of a user application by the processor, generate a stop and test indicator, in response to the generation of the stop and test indicator stop the execution of the user application and, if necessary, save a state of the at least one logic block of the processor;
- at least one scan chain, wherein the test controller is further configured to input a test stimulus for testing the at least one logic block of the processor into the at least one scan chain for a plurality of clock cycles and output test results out of the at least one scan chain;
- a pattern generator configured to generate the test stimulus;
- and
- a signature analyzer configured to generate at least one signature corresponding to the output results and comparing the at least one signature to a corresponding expected signature.
Dependencies are inferred from the claim text.