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AssigneeSyntest Technologies, Inc.
InventorsLaung-Terng (L.-T.) Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.
A unified test controller for testing or diagnosing a plurality of clock domains in a scan-based integrated circuit in selected self-test or scan-test mode, the unified test controller having a global scan enable (GSE) signal and a test clock, and each domain controlled by one system clock;
Dependencies are inferred from the claim text.