Automatic bit fail mapping for embedded memories with clock multipliers

A circuit for implementing at speed bit fail mapping of an embedded memory system having a BIST (Built In Self Testing) engine on a chip, comprising:

• an off-chip tester having a tester clock;
• the BIST engine using a high speed multiplied clock which is an asynchronous multiple of the tester clock to sequence the BIST engine for bit fail testing of the embedded memory system, said BIST engine generating a fail map data for capture at fail location latches of a diagnostic register device, the diagnostic fail data being stored in fail location latches at a time of recognizing said BIST fail test, and generating a signal for receipt by said off-chip tester to identify a BIST bit fail test for said tester;
• the circuit including BIST clock control logic, responsive to said generated signal, for pausing the BIST testing upon recognition of a fail of the embedded memory system, said BIST clock control logic gating off said high speed multiplied clock to BIST test latches and fail location latches of said diagnostic register;
• said off-chip tester asserting, for receipt by said circuit, a first signal in response to receiving said generated signal;
• said BIST clock control logic for automatically switching, in response to said received asserted first signal, said diagnostic register device to operate from a data capture mode controlled by the high speed multiplied clock to a serial transfer mode controlled by the tester clock,
• the circuit using the tester clock to read bit fail data out to the tester from said fail location latches of said diagnostic register device, and,
• said off-chip tester de-asserting said first signal for receipt by said BIST clock control logic when all fail data out from said fail location latches of said diagnostic register device are read;
• and
• said circuit, in response to said received de-asserted first signal, to resume data capture at said fail location latches of said diagnostic register device at said high speed multiplied clock from the point at which BIST testing was paused, wherein diagnostic bit fail data is extracted from said diagnostic register device without disturbing a state of said BIST or said embedded memory.

A circuit for enabling at speed bit fail mapping of an embedded Dynamic Random Access Memory (DRAM) system, the circuit comprising:

• a bit fail map data register having diagnostic latches used to store data on failing memory locations for the generation of a bit fail map in a data capture mode controlled by a high speed multiplied clock which is an asynchronous multiple of a slower tester clock, an on-chip clock multiplier provided for multiplying said slower tester clock of an off-chip ATE (Automatic Test Equipment) tester to produce said high speed multiplied clock;
• a first control latch that asserts a pause signal upon receiving a fail data signal indicating a mismatch comparison between expected data from the embedded memory system and actual data read from the embedded memory system, the bit fail map data being stored in said diagnostic latches at a time of recognizing a BIST bit fail test;
• a second control latch that is set upon receiving the pause signal from the first control latch and asserts a shift enable signal to enable a shift out of the data on failing memory locations from the bit fail map data register in a serial transfer mode controlled by the slower tester clock for the generation of a bit fail map, and,
• logic which includes the first and second control latches operable to pause a BIST (Built In Self Testing) engine at a point when a mismatch between BIST expected data and the actual data read from the DRAM is encountered, said logic causing said shifting out the bit fail data off the bit fail map data register using the slower ATE tester clock, and then resuming the BIST engine using the high speed multiplied clock to provide an at speed bit fail map,
• said pause signal of the first control latch pausing BIST engine test circuitry for testing the embedded memory system and enabling a continue/handshake signal from said off-chip ATE to enable the second control latch to assert the shift enable signal to enable a shift out of the data on failing memory locations from the bit fail map data register for the generation of a bit fail map,
• wherein the bit fail map data register includes fail location latches for storing the location of the fail upon recognition of the fail, and the logic that pauses the BIST engine also de-gates the slower ATE tester clock to the fail location registers, allowing the bit fail data to be shifted off the chip to the ATE tester at the slower ATE tester clock speed,
• wherein the first and second control latches include both master latches, which are clocked with function data with a function clock or with scan data with a scan clock, and slave latches which are updated with master latch data with a slave latch clock,
• wherein diagnostic bit fail data is extracted from said diagnostic register device without disturbing a state of said BIST or said embedded memory.