Generation of memory test patterns for DLL calibration

A system comprising:

• a memory chip including a plurality of storage locations to store data;
• a bus having a plurality of bit lines;
• and
• a processor connected to said memory chip via said bus and in communication therewith through said bus, wherein said processor is configured to perform the following:
• select a first group of bit lines from said bus to carry a first plurality of data patterns;
• select at least one of the remaining bit lines from said bus not within said first group to carry a second plurality of data patterns;
• transmit one or more of said first plurality of data patterns on said first group of bit lines,
• transmit one or more of said second plurality of data patterns on said at least one of the remaining bit lines;
• perform data write/read operations at one of said plurality of storage locations using said bus and said one or more of said first plurality of data patterns and said one or more of said second plurality of data patterns;
• and
• adjust a delay based on an accuracy of data read compared to data written in said data write/read operations.

A system comprising:

• a memory chip including a plurality of storage locations to store data;
• a bus having a plurality of bit lines;
• and
• a processor connected to said memory chip via said bus and in communication therewith through said bus, wherein said processor is configured to perform the following:
• select a first group of bit lines from said bus to carry a first plurality of data patterns;
• select at least one of the remaining bit lines from said bus not within said first group to carry a second data pattern;
• transmit one or more of said first plurality of data patterns on said first group of bit lines;
• transmit said second data pattern on said at least one of the remaining bit lines;
• and
• perform data write/read operations at one of said plurality of storage locations using said bus and said one or more of said first plurality of data patterns and said second data pattern ;
• and
• adjust a delay applied to a strobe signal based on an accuracy of data read compared to data written in said data write/read operations.

A method of operating a processor connected to a memory through a bus having a plurality of bit lines, said method comprising:

• selecting a first group of bit lines from said bus to carry a first plurality of data patterns;
• selecting at least one of the remaining bit lines from said bus not within said first group to carry a second plurality of data patterns;
• transmitting one or more of said first plurality of data patterns on said first group of bit lines,
• transmitting one or more of said second plurality of data patterns on said at least one of the remaining bit lines;
• performing data write/read operations at a data storage location in said memory using said bus and said one or more of said first plurality of data patterns and said one or more of said second plurality of data patterns;
• and
• adjusting a delay based on an accuracy of data read compared to data written in said data write/read operations.