Tracer, tracer embedded processor, and method for operating the tracer
AssigneeKabushiki Kaisha Toshiba
InventorKatsuyuki Kimura
Life of this patent
Estimating the term…
Abstract
A tracer includes a trace memory that is stored with trace information of the program execution status of a processor; trace information compression unit that compresses the trace information into a predetermined trace format, and stores the resulting compressed information in the trace memory piece by piece cyclically; and an address register that stores the last stored address of the trace memory, analyzes the content of the trace memory in reverse order to a program executed order, searches for a start or end of the trace format, and carries out trace analysis therefrom in the program executed order.
Claims20
A tracer comprising:
- a trace memory configured to store trace information of the program execution status of a processor;
- a trace information compression unit configured to compress the trace information into a predetermined variable length trace format, and to store the resulting compressed information in the trace memory cyclically piece by piece;
- and
- an address register configured to store the last stored address of the trace memory,
- wherein a capture of the trace information of each cycle is executed by successively reading the trace memory in an address increasing order from the last stored address and using information of an entire length of the trace information format, which is indicated by lower bits of the trace information, to find a next trace information stored address in a previous execution cycle.
A processor including a tracer comprising:
- a processor core module that includes a trace information output unit and reads in and executes processor instructions;
- a debug module that comprises a JTAG debugger interface and a tracer, which includes:
- a trace memory stored with trace information of the program execution status;
- a trace information compression unit, which compresses the trace information into a predetermined trace format and cyclically stores the resulting compressed trace information in the trace memory, piece by piece;
- and an address register, which stores the last stored address of the trace memory;
- and
- a bus connected between the processor core module and the debug module,
- wherein a capture of the trace information of each cycle is executed by successively reading the trace memory in the address increasing order from the last stored address and using information of an entire length of the trace information format, which is indicated by lower bits of the trace information, to find a next trace information stored address in a previous execution cycle.
A method for operating a tracer comprising:
- outputting trace information from a trace information output unit of a processor core module, which has executed a program, and inputting the trace information to a trace information compression unit during a trace operation;
- compressing the trace information into a variable-length trace storage format and successively storing the resulting compressed trace information in a trace memory;
- reading out content of the trace memory and the last stored address stored in an address register of the tracer by a JTAG debugger after completion of the trace operation, inputting an object/source code list of a program being executed by the processor core module to a trace analysis program storage unit of the JTAG debugger, and analyzing the content of the trace memory using a trace analysis program;
- and
- capturing the trace information of each cycle by successively reading the trace memory in the address increasing order from the last stored address and using information of an entire length of the trace information format, which is indicated by lower bits of the trace information, to find a next trace information stored address in a previous execution cycle.
Dependencies are inferred from the claim text.