Memory mirroring apparatus and method

A method for memory mirroring using a mirror memory having a memory fully buffered controller, comprising:

• employing the memory fully buffered controller to facilitate access to a plurality of memories in the mirror memory by a central processing unit (CPU);
• coupling a primary memory link interface in the memory fully buffered controller to a primary memory;
• detecting, in the memory fully buffered controller, whether a first data error exists in a first data output from the primary memory received through the primary memory link interface;
• attempting to correct the first data error if the first data error exists;
• detecting, in the memory fully buffered controller, whether a second data error exists in a second data output from the mirror memory;
• attempting to correct the second data error if the second data error exists;
• selecting, in the memory fully buffered controller, one of the first data output or the second data output to be applied to the CPU;
• and wherein the step of selecting, in the memory fully buffered controller, one of the first data output or the second data output to be applied to the CPU further comprises the step of selecting an uncorrected one of the first and second data outputs to be applied to the CPU if one of the first and second data outputs has been corrected by one of the first and second error logic, respectively.

A system for memory mirroring, comprising:

• first means for facilitating access to a plurality of memories in a mirror memory by a central processing unit (CPU);
• second means for establishing data communications between a primary memory and the CPU through the first means;
• selection means for selecting one of a first data output from the primary memory or a second data output from the mirror memory for application to the CPU based upon an existence of a data error in at least one of the first and second data outputs;
• and means for attempting to correct the data error in the at least one of the first and second data outputs if detected;
• and the selection means further comprises means for selecting an uncorrected one of the first and second data outputs to be applied to the CPU if one of the first and second data outputs has been corrected.