Methods and apparatus for reducing leakage current in a disabled SOI circuit
AssigneesSony Computer Entertainment Inc., International Business Machines Corporation, Toshiba America Electronic Components, Inc.
InventorsHiroshi Yoshihara, Sang Hoo Dhong, Osamu Takahashi, Takaaki Nakazato
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Abstract
Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.
Claims16
An apparatus, comprising:
- at least one digital circuit implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement, at least some of the transistors being referenced to a virtual ground node;
- at least one switch transistor coupled from the virtual ground node to a ground node for a power supply to the digital circuit;
- and
- a control circuit operable to:
- (i) enable the digital circuit by biasing the switch transistor ON such that a voltage potential of the virtual ground node is substantially equal to a voltage potential of the ground node;
- (ii) disable the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node such that the voltage potential of the virtual ground is substantially higher than the ground node;
- and (iii) control a substrate voltage of the SOI arrangement as a function of a threshold voltage of the at least one switch transistor.
An apparatus, comprising:
- a plurality of processors, each processor:
- (i) being capable of operative communication with a main memory, (ii) being implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement, and (iii) having at least some of its transistors referenced to a respective virtual ground node;
- at least one switch transistor coupled from each of the virtual ground nodes to a ground node of a power supply for the processors;
- and
- a control circuit operable to:
- (i) independently disable the processors by biasing gate terminal(s) of the respective switch transistor(s) below a voltage potential of the ground node;
- and (ii) control a substrate voltage of the SOI arrangement as a function of a threshold voltage of the at least one switch transistor.
A method, comprising:
- enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node;
- disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node;
- and
- controlling a substrate voltage of the SOI arrangement as a function of a threshold voltage of the at least one switch transistor.
Dependencies are inferred from the claim text.