Tracing through reset
AssigneeTexas Instruments Incorporated
InventorsManisha Agarwala, Lewis Nardini
Life of this patent
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Abstract
A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
Claims20
An apparatus for collecting trace data, comprising:
- a trace data input for receiving trace data from a data processor;
- first and second trace circuit portions for processing the received trace data, one of said first and second trace circuit portions coupled to said input, said first and second trace circuit portions cooperable for producing processed trace data for trace analysis;
- and
- reset logic coupled to said first and second trace circuit portions;
- wherein, in response to receipt of a reset signal under a first condition, said reset logic resets said first trace circuit portion without resetting said second trace circuit portion;
- and
- wherein, in response to receipt of said reset signal under a second condition, said reset logic resets said second trace circuit portion.
An integrated circuit apparatus, comprising:
- a data processor;
- a trace collector coupled to said data processor to receive trace data from said data processor, said trace collector including first and second trace circuit portions for processing the received trace data, said first and second trace circuit portions cooperable for producing processed trace data to be exported from the integrated circuit for trace analysis externally of the integrated circuit;
- and
- reset logic coupled to said first and second trace circuit portions;
- wherein, in response to receipt of a reset signal under a first condition, said reset logic resets said first trace circuit portion without resetting said second trace circuit portion;
- and
- wherein, in response to receipt of said reset signal under a second condition, said reset logic resets said second trace circuit portion.
Dependencies are inferred from the claim text.