Methods and apparatus for recognizing a subroutine call
AssigneeQUALCOMM Incorporated
InventorMichael William Morrow
Life of this patent
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Abstract
An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the next sequential address after the non-sequential change in program flow. The circuit is configured to compare the next sequential address and the contents of the register to determine whether the non-sequential change in program flow is a subroutine call.
Claims20
A method of recognizing a subroutine call, comprising:
- detecting a non-sequential change in program flow;
- retrieving a next sequential address after the detected non-sequential change in program flow;
- and
- comparing the next sequential address with the contents of a register to determine whether the non-sequential change is a subroutine call.
An apparatus in a processor for recognizing a subroutine call comprising:
- a circuit comprising:
- a first input for receiving contents of a register;
- a second input for receiving a non-sequential change in program flow;
- a third input for receiving the next sequential address after the non-sequential change in program flow wherein the circuit is configured to compare the next sequential address and the contents of the register to determine whether the non-sequential change in program flow is a subroutine call.
An apparatus for recognizing a subroutine call comprising:
- means for detecting a non-sequential change in program flow;
- means for retrieving a next sequential address after the detected non-sequential change in program flow;
- and
- means for comparing the next sequential address with the contents of a register to determine whether the non-sequential change is a subroutine call.
An apparatus for recognizing a subroutine call, comprising:
- a processor pipeline for processing instructions;
- and
- a circuit coupled to the processor pipeline, the circuit configured to receive contents of a register, an indication of a non-sequential change in program flow, and the next sequential address after the indication of the non-sequential change in program flow, the circuit configured to compare the contents of the link register with the next sequential address to determine whether the indication of a non-sequential change in program flow is a subroutine call.
Dependencies are inferred from the claim text.