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US 7,444,497 B2Granted
Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support
AssigneeIntel Corporation
InventorsSteven K. Reinhardt, Shubhendu S. Mukherjee, Joel S. Emer, Christopher T. Weaver
Life of this patent
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Abstract
A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.
Claims17
A method comprising:
- executing corresponding instruction threads in parallel as a leading thread and a trailing thread;
- speculatively saving a result from a first instruction executed in the leading thread and speculatively saving a result from a second instruction corresponding to the first instruction executed in the trailing thread to a memory having extensions for speculative storage;
- comparing the results saved in the memory;
- committing a single set of instructions based on the compared result;
- and
- deferring updates from one or more external agents to one or more memory locations accessed by the instruction threads until the single set of instructions has been committed.
3 more elements
An apparatus comprising:
- a means for executing parallel threads as a leading thread and a trailing thread;
- a means for speculatively saving the results from the executed threads in a memory having extensions for speculative storage;
- a means for comparing the results saved in the memory;
- a means for committing a single set of instructions based on the compared result;
- and
- a means for deferring one or more updates from one or more external agents to one or more memory locations accessed by the parallel threads until the single set of instructions has been committed.
3 more elements
An apparatus comprising:
- a thread execution logic to:
- execute parallel threads as a leading thread and a trailing thread;
- speculatively save the results from the executed threads in a memory having extensions for speculative storage;
- compare the results saved in the memory;
- and
- commit a single set of instructions based on the compared result;
- and
- a conflicting access detection mechanism to:
- defer one or more updates from one or more external agents to one or more memory locations accessed by the parallel threads until the single set of instructions has been committed.
6 more elements
Dependencies are inferred from the claim text.