Processor, virtual memory system, and virtual storing method
AssigneeKabushiki Kaisha Toshiba
InventorHidenori Matsuzaki
Life of this patent
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Abstract
A processor includes an address specifying unit that specifies an address range on a virtual storage area; an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range; a calculating unit that calculates the data corresponding to the address range, according to the instruction code set for the address range; a load instruction obtaining unit that obtains a load instruction for the specified address range; and a data output unit that supplies the data calculated by the calculating unit corresponding to the address range indicated by the load instruction, as data for the load instruction.
Claims10
A processor comprising:
- an address specifying unit that specifies an address range on a virtual storage area;
- an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range;
- a calculating unit that calculates the data corresponding to the specified address range, according to the instruction code set for the specified address range;
- a load instruction obtaining unit that obtains a load instruction for the specified address range;
- a data output unit that supplies the data calculated by the calculating unit corresponding to the specified address range indicated by the load instruction, as data for the load instruction;
- a data storing unit that stores the data calculated by the calculating unit in association with the specified address range;
- and
- a data managing unit that, when the load instruction is obtained, supplies the data stored into the data storing unit to the data output unit when the data corresponding to the specified address range indicated by the load instruction is stored in the data storing unit,
- wherein the data managing unit, when the load instruction is obtained, makes the calculating unit calculate the data corresponding to the specified address range when the data corresponding to the specified address range indicated by the load instruction is not stored in the data storing unit.
A virtual memory system comprising a first processor and a second processor, wherein each of the first processor and the second processor includes:
- an address specifying unit that specifies an address range on a virtual storage area,
- an instruction code setting unit that sets an instruction code for a process of deciding data corresponding to the specified address range,
- a calculating unit that calculates the data corresponding to the specified address range, according to the instruction code set for the specified address range,
- a load instruction obtaining unit that obtains a load instruction for the specified address range, and
- a data output unit that supplies the data calculated by the calculating unit corresponding to the specified address range indicated by the load instruction, as the data for the load instruction,
- the calculating unit of the first processor issues a load instruction to the second processor,
- the load instruction obtaining unit of the second processor obtains the load instruction from the first processor,
- the calculating unit of the second processor calculates the data for the load instruction obtained from the first processor,
- the data output unit of the second processor supplies the data obtained through the calculating unit of the second processor to the first processor, and
- the calculating unit of the first processor calculates the data, using the data obtained from the second processor.
A virtual storing method using a first processor and a second processor, comprising:
- specifying an address range on a virtual storage area in the first processor;
- setting an instruction code for a process of deciding data corresponding to the specified address range in the first processor;
- specifying an address range on a virtual storage area in the second processor;
- setting an instruction code for a process of deciding the data corresponding to the specified address range in the second processor;
- issuing a load instruction from the first processor to the second processor;
- specifying the address range indicated by the load instruction in the second processor;
- calculating the data for the address range according to the instruction code set for the address range, in the second processor;
- supplying the calculated data from the second processor to the first processor;
- calculating the data for the address range by using the supplied data in the first processor;
- obtaining the load instruction for the specified address range in the first processor;
- and
- supplying the data calculated for the address range indicated by the load instruction as the data for the obtained load instruction in the first processor.
Dependencies are inferred from the claim text.