Packet processor memory interface with memory conflict valve checking
AssigneeTeplin Application Limited Liability Company
InventorStephen Waller Melvin
Life of this patent
Estimating the term…
Abstract
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. When a potential memory conflict is detected, the values associated with the potentially conflicting memory operations are compared. In cases where the values match, no conflict is signaled. Such a value checking mechanism reduces the number of restarts needed in certain cases.
Claims12
An apparatus for interfacing a packet processing engine with a memory system comprising:
- a first data storage element storing information based upon a memory read comprising a first packet identifier, wherein said first data storage element comprises read data;
- a second data storage element storing information based upon a memory write comprising a second packet identifier, wherein said memory write comprises memory write data;
- read processing logic coupled to said first data storage element and said second data storage element, wherein said first data storage element is modified based on said memory read and said second data storage element is searched based on said memory read;
- write processing and conflict detection logic coupled to said first data storage element and said second data storage element, wherein said second data storage element is modified based on said memory write and said first data storage element is searched based on said memory write, and wherein a determination is made whether a memory conflict exists between said memory read and said memory write;
- logic for signaling a restart coupled to said write processing and conflict detection logic and utilizing said first associated packet identifier;
- wherein if a memory conflict is detected, said memory write data is compared to said read data and a restart is not signaled if said memory write data matches said read data.
A method of interfacing a packet processor with a memory system comprising the steps of:
- receiving a memory read comprising a first packet identifier from a packet processing engine;
- storing information based upon said memory read into a first data storage element;
- returning speculative read data to the packet processing engine responsive to said memory read, wherein said speculative read data is stored in said first data storage element;
- receiving a memory write comprising a second packet identifier from said packet processing engine, said memory write comprising memory write data;
- storing information based on said memory write into said second data storage element;
- searching said first data storage element using information based on said memory write and determining if a memory conflict exists;
- and
- if a memory conflict is detected, comparing said memory write data to said speculative read data and signaling a restart if said memory write data does not match said speculative read data.
Dependencies are inferred from the claim text.