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US 7,444,480 B2Granted
Processor, memory device, computer system, and method for transferring data
AssigneeKabushiki Kaisha Toshiba
InventorTatsunori Kanai
Life of this patent
Estimating the term…
Abstract
A processor connected to a memory device includes a random number generator that generates random numbers identical to random numbers generated in the memory device; an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory device to be accessed; and an after-operation-address sending unit that sends an after-operation-address indicating a result of the XOR operation.
Claims10
A processor connected to a memory device comprising:
- a random number generator that generates random numbers identical to random numbers generated in the memory device;
- an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory device to be accessed;
- an after-operation-address sending unit that sends an after-operation-address indicating a result of the XOR operation;
- an encryption unit that encrypts data sent by the processor with the address in the memory device for the data to obtain the encrypted data;
- and
- an encrypted data sending unit that sends the encrypted data,
- wherein the encryption unit obtains the encrypted data by permuting an array of multiple partial data contained in the data based on the address of the data.
4 more elements
A processor connected to a memory device comprising:
- a random number generator that generates random numbers identical to random numbers generated in the memory device;
- an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory device to be accessed;
- an after-operation-address sending unit that sends an after-operation-address indicating a result of the XOR operation;
- a cache memory that temporary stores data;
- and
- an access order determining unit that determines an access order of a continuous address of the memory device so as to store data per cache line stored in the cash memory, based on predetermined information,
- wherein the after-operation-address sending unit sends the after-operation-address in the determined access order.
4 more elements
A processor connected to a memory device comprising:
- a random number generator that generates random numbers identical to random numbers generated in the memory device;
- an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory device to be accessed;
- an after-operation-address sending unit that sends an after-operation-address indicating a result of the XOR operation;
- and
- a cache memory that temporary stores data;
- and
- an access order determining unit that determines an access order of multiple continuous addresses where data per cache line in the cache memory is stored, based on predetermined information,
- wherein the after-operation-address sending unit sends the after-operation-address in the determined access order.
5 more elements
A processor connected to a memory device comprising:
- a random number generator that generates random numbers identical to random numbers generated in the memory device;
- an XOR logic unit that performs a XOR operation of the random numbers and an address in the memory device to be accessed;
- an after-operation-address sending unit that sends an after-operation-address indicating a result of the XOR operation;
- and
- an encrypted data obtaining unit that obtains encrypted data encrypted with the address;
- and
- a decrypting unit that obtains data by decrypting the obtained encrypted data, with the address.
4 more elements
A memory device for storing data utilized by a processor, comprising:
- an after-operation-address obtaining unit that obtains, from the processor, an after-operation-address indicating a result of an XOR operation of an address in the memory device to be accessed by the processor and random numbers generated by the processor;
- a random number generator that generates random numbers identical to random numbers generated by the processor;
- an XOR logic unit that determines the address of the data by performing the XOR operation of the after-operation-address and the random numbers generated by the random number generator;
- a control unit that allows an access to a specified address;
- an encrypted data obtaining unit that obtains the encrypted data encrypted with the address of the data from the processor;
- and
- a decrypting unit that decrypts the encrypted data with the address specified by the XOR logic unit.
4 more elements
A computer system comprising:
- a processor that performs an operation;
- and
- a memory device that stores data utilized by the processor,
- wherein the processor includes
- a random number generator that generates random numbers identical to random numbers generated in the memory device;
- a first XOR logic unit that performs an XOR operation of the random numbers and address in the memory device to be accessed;
- and
- an after-operation-address sending unit that sends an after-operation-address indicating a result of the operation, and the memory device includes
- an after-operation-address obtaining unit that obtains the after-operation-address from the processor;
- a random number generator that generates random numbers identical to the random numbers;
- a second XOR logic unit that determines an address to be accessed by performing an XOR operation of the after-operation-address obtained by the after-operation-address obtaining unit and the random numbers generated by the random number generator of the memory device;
- and
- a control unit that allows an access to the specified address.
10 more elements
A method for transferring data between a processor and a memory device for storing data utilized by the operating processor, comprising:
- generating random numbers identical to random numbers generated in the memory device by the processor;
- performing, by the processor, an XOR operation of the generated random numbers and an address in the memory device to be accessed by the processor;
- sending an after-operation-address indicating a result of the operation;
- obtaining the after-operation-address from the processor by the memory device;
- generating random numbers which are identical to random numbers generated by the processor, by the memory device;
- determining an address to be accessed by the memory device as performing the XOR operation of the after-operation-address and the random number generated by the memory device;
- and
- allowing an access to the address specified by the memory device.
5 more elements
Dependencies are inferred from the claim text.