Semiconductor integrated circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMasaya Sumita
Life of this patent
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Abstract
It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.
Claims14
A semiconductor integrated circuit having a cache capability, comprising:
- a translation look side buffer (TLB) and a cache, wherein,
- said cache comprises a cache memory index (TAG) memory module and a cache data memory module, and said TAG memory module comprises an input section, wherein said TAG memory module is immediately adjacent said TLB,
- a part connected to said TAG memory module, said part comprising a line connected between said TLB and said input section of said TAG memory module, wherein said input section of said TAG memory module is located immediately adjacent said TLB,
- a bus area located between said cache and said TLB, wherein said cache data memory module comprises an output section, and an output signal line connected to said output section of said cache data memory module and passes through the bus area,
- an amplifier that is connected to said output signal line and is located substantially where said output signal line goes out of said bus area, and
- a power supply line and a grounding line located in a layer under or above said output signal line, wherein
- said power supply line and said grounding line intersect said output signal line.
A semiconductor integrated circuit having a cache capability, comprising:
- a translation look aside buffer (TLB),
- a cache comprising a cache memory index (TAG) memory module and a cache data memory module, said TAG memory module comprises an input section, and said input section has a side comprising input section connection nodes closest to a side of said TLB comprising TLB connection nodes,
- a line connecting the connection nodes of the closest sides of the input section and the TLB,
- a bus area located between said cache and said TLB, wherein said cache data memory module comprises an output section, and an output signal line connected to said output section of said cache data memory module passes through the bus area,
- an amplifier that is connected to said output signal line and is located substantially where said output signal line goes out of said bus area, and
- a power supply line and a grounding line located in a layer under or above said output signal line, wherein
- said power supply line and said grounding line intersect said output signal line.
Dependencies are inferred from the claim text.