Speculative memory accesses in a proximity communication-based off-chip cache memory architecture
AssigneeSun Microsystems, Inc.
InventorsMichael J. Koster, Brian W. O'Krafka
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Abstract
A proximity interconnect module includes a plurality of processors operatively connected to a plurality of off-chip cache memories by proximity communication. Due to the high bandwidth capability of proximity interconnect, when an off-chip cache memory is searched for requested data, either the requested data is at the same time searched for in on-chip cache memories of the proximity interconnect module or the requested data is at the same time retrieved from main memory. This reduces latency by reducing serial operations.
Claims18
A system, comprising:
- a first processor having a first on-chip cache memory;
- a second processor having a second on-chip cache memory, wherein the second processor is operatively connected to the first processor and a third processor by proximity communication, the third processor having a third on-chip cache memory, wherein the third processor is operatively connected to the first processor and the second processor by proximity communication;
- and
- a first off-chip cache memory operatively connected to the first processor and the second processor by proximity communication,
- wherein, in response to a cache miss for requested data in the first on-chip cache memory, the system is configured to search for the requested data in the first off-chip cache memory in parallel with searching for the requested data in the second on-chip cache memory and the third on-chip cache memory.
A method of performing computer system operations, comprising:
- searching for requested data in a first on-chip cache memory of a first processor;
- and
- when the requested data is not found in the first on-chip cache memory, searching for the requested data in a first off-chip cache memory in parallel with searching for the requested data in a second on-chip cache memory and a third on-chip cache memory of a third processor,
- wherein the first processor, the second processor, and the third processor are operatively connected by proximity communication, and the first off-chip cache memory are is operatively connected to the first processor and the second processor by proximity communication.
A system, comprising:
- a proximity interconnect module;
- a plurality of processors disposed on the proximity interconnect module, the plurality of processors each having an on-chip cache memory;
- and
- a plurality of off-chip cache memories disposed on the proximity interconnect module and operatively connected to the plurality of processors by proximity communication,
- wherein, in response to a cache miss for requested data in a first on-chip cache memory of a first processor of the plurality of processors, the system is configured to search for the requested data in a first off-chip cache memory of the plurality of off-chip cache memories in parallel with searching for the requested data in all other on-chip cache memories of the on-chip cache memories.
A system, comprising:
- a proximity interconnect module;
- a plurality of processors disposed on the proximity interconnect module, the plurality of processors each having an on-chip cache memory;
- a plurality of off-chip cache memories disposed on the proximity interconnect module and operatively connected to the plurality of processors by proximity communication;
- and
- a main memory operatively connected to the plurality of processors and the proximity interconnect module,
- wherein, in response to a cache miss for requested data in one of the on-chip cache memories, the system is configured to search for the requested data in one off-chip cache memory of the plurality of off-chip cache memories in parallel with searching for the requested data in all of the other on-chip cache memories of the plurality of other processors in the system.
Dependencies are inferred from the claim text.