Apparatus and method for writing a sparsely populated cache line to memory

A processor bus system, comprising:

• a processor bus comprising address signals, data signals, and request signals;
• a processor, coupled to said processor bus, which controls said address signals and said request signals to request a sparse write-combined memory write transaction and to provide a plurality of doubleword enable bits, and which controls said data signals to provide data for said sparse write-combined memory write transaction, wherein said sparse memory write transaction comprises sending an entire cache line to memory, and wherein individual data elements within said cache line are enabled to be written to said memory with doubleword granularity;
• and
• a bus agent, coupled to said processor bus, which writes portions of said data to a memory location selected by said plurality of doubleword enable bits, wherein said corresponding plurality of enable bits determines which doublewords of said cache line are to be written to said memory;
• wherein said processor asserts a first part comprising an address and a memory line write request on said address signals and said request signals, respectively, and asserts a second part comprising a sparse write-combined memory write transaction request and said plurality of doubleword enable bits on said address signals and said request signals, respectively;
• and
• wherein said processor replaces an attribute value and byte enable bits on said address signals of said second part with said plurality of doubleword enable bits.

A method of performing a sparse write-combined write transaction, comprising:

• providing, by a processor, an address and a request for a memory write transaction, wherein the memory write transaction comprises sending an entire cache line to memory, and wherein individual data elements within the cache line are enabled to be written to the memory with doubleword granularity;
• indicating, by the processor, that the memory write transaction is a sparse write-combined write transaction, said indicating comprising:
• asserting, by the processor, a first transaction part including an address and a request for the memory write transaction
• replacing an attribute value and byte enable bits on address signals of a second transaction part with a plurality of doubleword enable bits;
• and
• asserting, by the processor, the second transaction part including a sparse line write command and the plurality of doubleword enable bits, wherein the plurality of doubleword enable bits determines which doublewords of the cache line are to be written to the memory;
• and
• providing, by the processor, data for the sparse write-combined write transaction.