Retrieving data blocks with reduced linear addresses
AssigneeIntel Corporation
InventorsStephan J. Jourdan, Chris E. Yunker, Pierre Michaud
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Abstract
Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.
Claims26
A method of processing addresses, comprising:
- receiving a full linear address of an instruction;
- and
- reducing a size of the full linear address to obtain a reduced linear address by using a number of bits of the full linear address to generate a number of bits less than the used number of bits of the full linear address;
- and
- retrieving a data block from a data array if the reduced linear address corresponds to a tag in a tag array, the tag array being associated with the data array, wherein the data block includes an address having a size that equals a size of the reduced linear address.
A method of retrieving data, comprising:
- receiving a full linear address of an instruction;
- reducing a size of the full linear address to obtain a reduced linear address, the reducing including hashing a subset of the full linear address to generate a number of bits less than the used number of bits of the full linear address;
- isolating one or more cache line offset bits of the full linear address and one or more set index bits of the full linear address from the hashing;
- and
- retrieving a data block from a data array if the reduced linear address corresponds to a tag in a tag array, the tag array being associated with the data array, wherein the data block includes an address having a size that equals a size of the reduced linear address.
An address processing unit comprising:
- a data structure having a data array and a tag array;
- a reduction module to reduce a size of a full linear address of an instruction to obtain a reduced linear address said reduction module to use bits of the full linear address to generate a number of bits for the reduced linear address less than the used number of bits of the full linear address;
- and
- a retrieval module to retrieve a data block from the data array if the reduced linear address corresponds to a tag in the tag array, the tag array being associated with the data array, wherein the data block includes an address having a size that equals a size of the reduced linear address.
A computer system comprising:
- a random access memory;
- a bus coupled to the memory;
- and
- a processor coupled to the bus, the processor to receive an instruction from the memory and including an address processing unit having a data structure, a reduction module and a retrieval module, the data structure having a data array and a tag array, the reduction module to reduce a size of a full linear address of the instruction to obtain a reduced linear address, said reduction module to use bits of the full linear address to generate a number of bits for the reduced linear address less than the used number of bits of the full linear address, the retrieval module to retrieve a data block from the data array if the reduced linear address corresponds to a tag in the tag array, the tag array being associated with the data array, wherein the data block includes an address having a size that equals a size of the reduced linear address.
Dependencies are inferred from the claim text.