SRAM bus architecture and interconnect to an FPGA
AssigneeActel Corporation
InventorWilliam C. Plants
Life of this patent
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Abstract
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.
Claims8
An architecture for a programmable integrated circuit including:
- a first group of logic function modules associated with a first group of FPGA routing conductors;
- a second group of logic function modules spaced apart from said first group of logic function modules and associated with a second group of FPGA routing conductors;
- a plurality of dedicated SRAM blocks, each SRAM block having address busses, data busses and control lines;
- a plurality of pass-through interconnect conductors spanning each SRAM block, each of said plurality of said pass-through interconnect conductors having a first end and a second end;
- a first plurality of user-programmable interconnect elements coupled between first ends of the pass-through interconnect conductors and ones of the first group of FPGA routing conductors;
- a second plurality of user-programmable interconnect elements coupled between second ends of the pass-through interconnect conductors and ones of the second group of FPGA routing conductors;
- a multi-conductor address bus disposed in one of said plurality of dedicated SRAM blocks forming first intersections with said plurality of pass-through interconnect conductors;
- a multi-conductor data bus disposed in one of said plurality of dedicated SRAM blocks forming second intersections with said plurality of pass-through interconnect conductors;
- a multi-conductor group of control signal lines disposed in one of said plurality of dedicated SRAM blocks forming third interconnect intersections with said plurality of pass-through interconnect conductors;
- and
- user-programmable interconnect elements disposed at selected ones of said first, second and third intersections.
Dependencies are inferred from the claim text.