Back to results
US 7,444,454 B2Granted
Systems and methods for interconnection of multiple FPGA devices
AssigneeL-3 Communications Integrated Systems L.P.
InventorsJerry W. Yancey, Yea Z. Kuo
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeL-3 Communications Integrated Systems L.P.
InventorsJerry W. Yancey, Yea Z. Kuo
Estimating the term…
Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.
An ASIC array, comprising:
Signal processing circuitry comprising two or more ASIC devices, each one of said two or more ASIC devices being a separate chip from the other of said two or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, a reader interface of said packet router of each one of said two or more ASIC devices being coupled to a respective writer interface of each respective packet router of each of the other of said two or more ASIC devices by a separate respective duplex data communication link so as to form a direct serial interconnection between each two of said two or more ASIC devices;
A method of routing data packets between three or more ASIC devices of an ASIC array that each comprise a first serial connection and a second serial connection, said method comprising:
A method of processing signals using signal processing circuitry comprising two or more ASIC devices, each one of said two or more ASIC devices being a separate chip from the other of said two or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router having at least one reader interface configured as a packet source and multiple writer interfaces configured as packet destinations or having at least one writer interface configured as a packet destination and multiple reader interfaces configured as packet sources, and said method comprising transferring at least one data packet from each said packet router of each one of said two or more ASIC devices to each respective packet router of each of the other of said two or more ASIC devices by a separate respective duplex data communication link that forms a direct serial interconnection between each two of said two or more ASIC devices, said separate respective duplex data communication link being coupled between a reader interface of said packet router of one of said two or more ASIC devices and a respective writer interface of another of said two or more ASIC devices and wherein said method further comprises:
Signal processing circuitry comprising three or more ASIC devices, each one of said three or more ASIC devices being a separate chip from the other of said three or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router of each one of said three or more ASIC devices having multiple reader interfaces and multiple writer interfaces, said packet router of each one of said three or more ASIC devices also being coupled to each respective packet router of each one of the other of said three or more ASIC devices by a separate respective duplex data communication link so as to form a direct interconnection between each two of said three or more ASIC devices;
Signal processing circuitry comprising three or more ASIC devices coupled together by one or more duplex serial data communication links and being configured so that any given one of said three or more ASIC devices may bi-directionally communicate across a duplex serial data communication link with any given other one of said three or more ASIC devices, said duplex serial data communication link comprising no more than two serial connections;
A method of processing signals using three or more ASIC devices, said method comprising bi-directionally communicating signals across a duplex serial data communication link from any given one of said three or more ASIC devices to any given other one of said three or more ASIC devices, said duplex serial data communication link comprising no more than two serial connections;
A method of processing signals using signal processing circuitry comprising three or more ASIC devices, each one of said three or more ASIC devices being a separate chip from the other of said three or more ASIC devices and comprising a packet router contained entirely within said respective ASIC device, said packet router having multiple reader interfaces configured as packet sources and multiple writer interfaces configured as packet destinations, and said method comprising:
Dependencies are inferred from the claim text.